| /drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.c | 205 .dram_clock_change_latency_us = 23.84,
299 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()
307 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
319 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; in calculate_wm_set_for_vlevel()
380 if ((int)(dcn3_01_soc.dram_clock_change_latency_us * 1000) in dcn301_fpu_update_bw_bounding_box()
383 dcn3_01_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000.0; in dcn301_fpu_update_bw_bounding_box()
403 dcn3_01_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; in dcn301_fpu_init_soc_bounding_box()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | dcn31_fpu.c | 459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
474 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
659 if ((int)(dcn3_1_soc.dram_clock_change_latency_us * 1000) in dcn31_update_bw_bounding_box()
662 dcn3_1_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000; in dcn31_update_bw_bounding_box()
720 if ((int)(dcn3_15_soc.dram_clock_change_latency_us * 1000) in dcn315_update_bw_bounding_box()
723 dcn3_15_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000; in dcn315_update_bw_bounding_box()
800 if ((int)(dcn3_16_soc.dram_clock_change_latency_us * 1000) in dcn316_update_bw_bounding_box()
803 dcn3_16_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000; in dcn316_update_bw_bounding_box()
821 return (int)(soc->dram_clock_change_latency_us * pix_clk_100hz * bpp in dcn_get_approx_det_segs_required_for_pstate()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | dcn30_fpu.c | 167 .dram_clock_change_latency_us = 404,
296 context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0) in dcn30_fpu_update_soc_for_wm_a()
297 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_update_soc_for_wm_a()
341 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_calculate_wm_and_dlg()
366 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_calculate_wm_and_dlg()
412 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_fpu_calculate_wm_and_dlg()
433 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_fpu_calculate_wm_and_dlg()
515 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_fpu_calculate_wm_and_dlg()
632 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_find_dummy_latency_index_for_fw_based_mclk_switch()
661 double pstate_latency_us = base->ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn3_fpu_build_wm_range_table()
[all …]
|
| A D | display_rq_dlg_calc_30.c | 1237 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml_rq_dlg_get_dlg_params()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| A D | dcn351_fpu.c | 218 .dram_clock_change_latency_us = 34,
357 if ((int)(dcn3_51_soc.dram_clock_change_latency_us * 1000) in dcn351_update_bw_bounding_box_fpu()
360 dcn3_51_soc.dram_clock_change_latency_us = in dcn351_update_bw_bounding_box_fpu()
365 dcn3_51_soc.dram_clock_change_latency_us = in dcn351_update_bw_bounding_box_fpu()
425 …dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_51_soc.dram_clock_change_laten… in dcn351_update_bw_bounding_box_fpu()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| A D | dcn35_fpu.c | 180 .dram_clock_change_latency_us = 34.0,
323 if ((int)(dcn3_5_soc.dram_clock_change_latency_us * 1000) in dcn35_update_bw_bounding_box_fpu()
326 dcn3_5_soc.dram_clock_change_latency_us = in dcn35_update_bw_bounding_box_fpu()
331 dcn3_5_soc.dram_clock_change_latency_us = in dcn35_update_bw_bounding_box_fpu()
392 …dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_5_soc.dram_clock_change_latenc… in dcn35_update_bw_bounding_box_fpu()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| A D | dcn321_fpu.c | 155 .dram_clock_change_latency_us = 400,
638 if ((int)(dcn3_21_soc.dram_clock_change_latency_us * 1000) in dcn321_update_bw_bounding_box_fpu()
641 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
642 dcn3_21_soc.dram_clock_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
667 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
668 dcn3_21_soc.dram_clock_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
|
| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_socbb.h | 71 uint32_t dram_clock_change_latency_us; member
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| A D | dcn302_fpu.c | 155 .dram_clock_change_latency_us = 404,
355 dcn3_02_soc.dram_clock_change_latency_us = in dcn302_fpu_init_soc_bounding_box()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn10/ |
| A D | dcn10_fpu.c | 122 .dram_clock_change_latency_us = 17.0,
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| A D | dcn303_fpu.c | 154 .dram_clock_change_latency_us = 404,
373 dcn3_03_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; in dcn303_fpu_init_soc_bounding_box()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 323 .dram_clock_change_latency_us = 404.0,
434 .dram_clock_change_latency_us = 404.0,
545 .dram_clock_change_latency_us = 45.0,
759 .dram_clock_change_latency_us = 23.84,
2014 if ((int)(bb->dram_clock_change_latency_us * 1000) in dcn20_patch_bounding_box()
2017 bb->dram_clock_change_latency_us = in dcn20_patch_bounding_box()
2089 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; in dcn20_validate_bandwidth_fp()
2127 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; in dcn20_validate_bandwidth_fp()
2213 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()
2221 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
[all …]
|
| A D | display_rq_dlg_calc_20.c | 1083 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml20_rq_dlg_get_dlg_params()
|
| A D | display_rq_dlg_calc_20v2.c | 1084 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml20v2_rq_dlg_get_dlg_params()
|
| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_translation_helper.c | 379 p->in_states->state_array[0].dram_clock_change_latency_us = 400; in dml2_init_soc_states()
415 p->in_states->state_array[0].dram_clock_change_latency_us = 400; in dml2_init_soc_states()
450 p->in_states->state_array[0].dram_clock_change_latency_us = 400; in dml2_init_soc_states()
491 if (dml2->config.bbox_overrides.dram_clock_change_latency_us) { in dml2_init_soc_states()
492 p->in_states->state_array[i].dram_clock_change_latency_us = in dml2_init_soc_states()
493 dml2->config.bbox_overrides.dram_clock_change_latency_us; in dml2_init_soc_states()
733 out->state_array[i].dram_clock_change_latency_us = dc->dml.soc.dram_clock_change_latency_us; in dml2_translate_soc_states()
|
| A D | dml2_wrapper.c | 192 …lk_change_latencies[i] = dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us; in calculate_lowest_supported_state_for_temp_read()
197 …dml2->v20.dml_core_ctx.states.state_array[j].dram_clock_change_latency_us = s_global->dummy_pstate… in calculate_lowest_supported_state_for_temp_read()
222 …dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us = s->uclk_change_latenci… in calculate_lowest_supported_state_for_temp_read()
|
| A D | dml2_wrapper.h | 194 double dram_clock_change_latency_us; member
|
| A D | display_mode_util.c | 644 …print("DML: state_bbox: dram_clock_change_latency_us = %f\n", state->dram_clock_change_latency_us); in dml_print_soc_state_bounding_box()
|
| A D | display_mode_core_structs.h | 300 dml_float_t dram_clock_change_latency_us; member
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 176 .dram_clock_change_latency_us = 400,
291 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
2346 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
2384 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
2512 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
2533 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
2625 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
3080 if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000) in dcn32_update_bw_bounding_box_fpu()
3083 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn32_update_bw_bounding_box_fpu()
3084 dcn3_2_soc.dram_clock_change_latency_us = in dcn32_update_bw_bounding_box_fpu()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_structs.h | 235 double dram_clock_change_latency_us; member
|
| A D | dml1_display_rq_dlg_calc.c | 1307 mode_lib->soc.dram_clock_change_latency_us in dml1_rq_dlg_get_dlg_params()
1323 (double) mode_lib->soc.dram_clock_change_latency_us); in dml1_rq_dlg_get_dlg_params()
|
| A D | display_mode_vba.c | 358 mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us; in fetch_socbb_params()
359 mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us; in fetch_socbb_params()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 228 .dram_clock_change_latency_us = 250.0,
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.c | 1131 mode_lib->soc.dram_clock_change_latency_us in dml_rq_dlg_get_dlg_params()
|