| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_policy.c | 37 entry->dram_speed_mts = bw_on_sdp / (socbb->num_chans * in get_optimal_ntuple()
45 } else if (entry->dram_speed_mts > 0) { in get_optimal_ntuple()
104 table->state_array[index].dram_speed_mts = (int)entry->dram_speed_mts; in insert_entry_into_table_sorted()
156 if (p->in_states->state_array[i].dram_speed_mts > 0) in dml2_policy_build_synthetic_soc_states()
180 s->entry.dram_speed_mts = 0; in dml2_policy_build_synthetic_soc_states()
191 s->entry.dram_speed_mts = p->in_states->state_array[i].dram_speed_mts; in dml2_policy_build_synthetic_soc_states()
206 s->entry.dram_speed_mts = 0; in dml2_policy_build_synthetic_soc_states()
215 s->entry.dram_speed_mts = 0; in dml2_policy_build_synthetic_soc_states()
235 … if (p->in_states->state_array[j].dram_speed_mts >= p->out_states->state_array[i].dram_speed_mts) { in dml2_policy_build_synthetic_soc_states()
236 p->out_states->state_array[i].dram_speed_mts = p->in_states->state_array[j].dram_speed_mts; in dml2_policy_build_synthetic_soc_states()
[all …]
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| A D | dml2_translation_helper.c | 369 p->in_states->state_array[0].dram_speed_mts = 100 * transactions_per_mem_clock; in dml2_init_soc_states()
389 p->in_states->state_array[1].dram_speed_mts = 1125 * transactions_per_mem_clock; in dml2_init_soc_states()
405 p->in_states->state_array[0].dram_speed_mts = 100 * transactions_per_mem_clock; in dml2_init_soc_states()
425 p->in_states->state_array[1].dram_speed_mts = 1000 * transactions_per_mem_clock; in dml2_init_soc_states()
440 p->in_states->state_array[0].dram_speed_mts = 97 * transactions_per_mem_clock; //100 * in dml2_init_soc_states()
460 p->in_states->state_array[1].dram_speed_mts = 1125 * transactions_per_mem_clock; in dml2_init_soc_states()
536 p->in_states->state_array[i].dram_speed_mts = in dml2_init_soc_states()
572 if (p->in_states->state_array[i].dram_speed_mts > max_uclk_mhz) in dml2_init_soc_states()
573 max_uclk_mhz = (int)p->in_states->state_array[i].dram_speed_mts; in dml2_init_soc_states()
598 p->out_states->state_array[i].dram_speed_mts = p->in_states->state_array[i].dram_speed_mts; in dml2_init_soc_states()
[all …]
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| A D | dml2_wrapper.c | 214 …>v20.dml_core_ctx.states.state_array[result].dram_speed_mts < s_global->dummy_pstate_table[i].dram… in calculate_lowest_supported_state_for_temp_read()
415 …clk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts; in dml2_validate_and_build_resource()
473 …clk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts; in dml2_validate_and_build_resource()
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| A D | dml2_wrapper.h | 164 unsigned int dram_speed_mts; /*which is based on wck_ratio*/ member
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| A D | display_mode_util.c | 633 dml_print("DML: state_bbox: dram_speed_mts = %f\n", state->dram_speed_mts); in dml_print_soc_state_bounding_box()
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| A D | display_mode_core_structs.h | 289 dml_float_t dram_speed_mts; member
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| /drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| A D | dcn321_fpu.c | 118 .dram_speed_mts = 16000.0,
176 } else if (entry->dram_speed_mts > 0) { in get_optimal_ntuple()
301 if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) || in remove_inconsistent_entries()
437 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
447 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
469 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
480 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
563 table[i].dram_speed_mts == table[i + 1].dram_speed_mts) in build_synthetic_soc_states()
844 if (!dram_speed_mts[i] && i > 0) in dcn321_update_bw_bounding_box_fpu()
845 dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts; in dcn321_update_bw_bounding_box_fpu()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| A D | dcn303_fpu.c | 197 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box() local
290 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_fpu_update_bw_bounding_box()
294 dram_speed_mts[num_states++] = in dcn303_fpu_update_bw_bounding_box()
304 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_fpu_update_bw_bounding_box()
310 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn303_fpu_update_bw_bounding_box()
328 dcn3_03_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; in dcn303_fpu_update_bw_bounding_box()
351 if (dcn3_03_soc.clock_limits[i].dram_speed_mts > 1700) in dcn303_fpu_update_bw_bounding_box()
354 if (dcn3_03_soc.clock_limits[i].dram_speed_mts >= 1500) { in dcn303_fpu_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| A D | dcn302_fpu.c | 201 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box() local
285 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_fpu_update_bw_bounding_box()
289 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
298 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_fpu_update_bw_bounding_box()
304 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
322 dcn3_02_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; in dcn302_fpu_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| A D | dcn351_fpu.c | 104 .dram_speed_mts = 3200.0,
117 .dram_speed_mts = 6400.0,
130 .dram_speed_mts = 7500.0,
143 .dram_speed_mts = 7500.0,
156 .dram_speed_mts = 8533.0,
169 .dram_speed_mts = 8533.0,
182 .dram_speed_mts = 8533.0,
195 .dram_speed_mts = 8533.0,
322 clock_limits[i].dram_speed_mts = in dcn351_update_bw_bounding_box_fpu()
404 …ml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_m… in dcn351_update_bw_bounding_box_fpu()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.c | 116 .dram_speed_mts = 2400.0,
128 .dram_speed_mts = 2400.0,
140 .dram_speed_mts = 4267.0,
152 .dram_speed_mts = 4267.0,
164 .dram_speed_mts = 4267.0,
354 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in dcn301_fpu_update_bw_bounding_box()
394 …_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; in dcn301_fpu_set_wm_ranges()
395 ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; in dcn301_fpu_set_wm_ranges()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 233 .dram_speed_mts = 8960.0,
244 .dram_speed_mts = 11104.0,
255 .dram_speed_mts = 14000.0,
344 .dram_speed_mts = 8960.0,
455 .dram_speed_mts = 1069.0,
466 .dram_speed_mts = 1324.0,
477 .dram_speed_mts = 1670.0,
488 .dram_speed_mts = 2000.0,
499 .dram_speed_mts = 2000.0,
510 .dram_speed_mts = 2000.0,
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | dcn30_fpu.c | 429 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts) in dcn30_fpu_calculate_wm_and_dlg()
504 if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) { in dcn30_fpu_calculate_wm_and_dlg()
505 context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts; in dcn30_fpu_calculate_wm_and_dlg()
572 unsigned int *dram_speed_mts) in dcn30_fpu_update_bw_bounding_box() argument
585 dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; in dcn30_fpu_update_bw_bounding_box()
700 base->bw_params->dummy_pstate_table[0].dram_speed_mts = 1600; in dcn3_fpu_build_wm_range_table()
702 base->bw_params->dummy_pstate_table[1].dram_speed_mts = 8000; in dcn3_fpu_build_wm_range_table()
704 base->bw_params->dummy_pstate_table[2].dram_speed_mts = 10000; in dcn3_fpu_build_wm_range_table()
706 base->bw_params->dummy_pstate_table[3].dram_speed_mts = 16000; in dcn3_fpu_build_wm_range_table()
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| A D | dcn30_fpu.h | 61 unsigned int *dram_speed_mts);
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 139 .dram_speed_mts = 18000.0,
408 } else if (entry->dram_speed_mts > 0) { in get_optimal_ntuple()
2759 if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) || in remove_inconsistent_entries()
2895 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
2905 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
2927 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
2938 entry.dram_speed_mts = 0; in build_synthetic_soc_states()
3019 table[i].dram_speed_mts == table[i + 1].dram_speed_mts) in build_synthetic_soc_states()
3294 if (!dram_speed_mts[i] && i > 0) in dcn32_update_bw_bounding_box_fpu()
3295 dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts; in dcn32_update_bw_bounding_box_fpu()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| A D | dcn35_clk_mgr.c | 916 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]); in dcn35_clk_mgr_helper_populate_bw_params() local
918 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_speed_mts) { in dcn35_clk_mgr_helper_populate_bw_params()
919 max_dram_speed_mts = dram_speed_mts; in dcn35_clk_mgr_helper_populate_bw_params()
928 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]); in dcn35_clk_mgr_helper_populate_bw_params() local
930 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_speed_mts) { in dcn35_clk_mgr_helper_populate_bw_params()
931 min_dram_speed_mts = dram_speed_mts; in dcn35_clk_mgr_helper_populate_bw_params()
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_socbb.h | 31 uint32_t dram_speed_mts; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 149 .dram_speed_mts = 2000.0,
160 .dram_speed_mts = 3600.0,
171 .dram_speed_mts = 6800.0,
182 .dram_speed_mts = 14000.0,
194 .dram_speed_mts = 14000.0,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| A D | dcn35_fpu.c | 288 clock_limits[i].dram_speed_mts = in dcn35_update_bw_bounding_box_fpu()
371 …ml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_m… in dcn35_update_bw_bounding_box_fpu()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | dcn31_fpu.c | 632 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * in dcn31_update_bw_bounding_box()
700 …dcn3_15_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->ent… in dcn315_update_bw_bounding_box()
772 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * in dcn316_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | clk_mgr.h | 255 unsigned int dram_speed_mts; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 2104 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box() local
2197 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn30_update_bw_bounding_box()
2201 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn30_update_bw_bounding_box()
2210 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn30_update_bw_bounding_box()
2216 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn30_update_bw_bounding_box()
2221 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts); in dcn30_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_structs.h | 163 double dram_speed_mts; member
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| A D | display_mode_vba.c | 382 mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()
403 mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | dcn314_fpu.c | 241 …clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_… in dcn314_update_bw_bounding_box_fpu()
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