Searched refs:dsc_clock_en (Results 1 – 7 of 7) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dsc/dcn35/ |
| A D | dcn35_dsc.c | 80 int dsc_clock_en; in dsc35_enable() local
94 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc35_enable()
96 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { in dsc35_enable()
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| /drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| A D | dcn401_dsc.c | 99 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); in dsc401_read_state()
141 int dsc_clock_en; in dsc401_enable() local
147 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc401_enable()
149 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { in dsc401_enable()
166 int dsc_clock_en; in dsc401_disable() local
170 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc401_disable()
171 if (!dsc_clock_en) { in dsc401_disable()
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| /drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| A D | dcn20_dsc.c | 146 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); in dsc2_read_state()
222 int dsc_clock_en; in dsc2_enable() local
228 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc2_enable()
230 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { in dsc2_enable()
247 int dsc_clock_en; in dsc2_disable() local
251 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc2_disable()
252 if (!dsc_clock_en) { in dsc2_disable()
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| /drivers/gpu/drm/amd/display/dc/dsc/ |
| A D | dsc.h | 56 uint32_t dsc_clock_en; member
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| A D | dcn35_hwseq.c | 886 s.dsc_clock_en && s.dsc_fw_en) in dcn35_init_pipes()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 657 s.dsc_clock_en, in dcn10_log_hw_state()
1716 s.dsc_clock_en && s.dsc_fw_en) in dcn10_init_pipes()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_debugfs.c | 1584 dsc_state.dsc_clock_en); in dp_dsc_clock_en_read()
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