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Searched refs:dsc_dpcd (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_dp.c1408 if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) in intel_dp_has_dsc()
1488 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, in intel_dp_mode_valid()
1905 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & in intel_dp_dsc_compute_params()
2113 u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); in intel_dp_dsc_bpp_step_x16()
2402 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, in intel_dp_dsc_compute_config()
4120 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in intel_dp_read_dsc_dpcd()
4122 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd, in intel_dp_read_dsc_dpcd()
4132 dsc_dpcd); in intel_dp_read_dsc_dpcd()
4143 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); in intel_dp_get_dsc_sink_cap()
4152 connector->dp.dsc_dpcd); in intel_dp_get_dsc_sink_cap()
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A Dintel_display_debugfs.c929 str_yes_no(drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))); in i915_dsc_fec_support_show()
931 str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, in i915_dsc_fec_support_show()
933 str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, in i915_dsc_fec_support_show()
935 str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, in i915_dsc_fec_support_show()
938 drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd)); in i915_dsc_fec_support_show()
940 drm_dp_dsc_sink_max_slice_count((connector->dp.dsc_dpcd), intel_dp_is_edp(intel_dp))); in i915_dsc_fec_support_show()
A Dintel_display_types.h547 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; member
A Dintel_dp_mst.c475 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, in mst_stream_dsc_compute_link_config()
/drivers/gpu/drm/display/
A Ddrm_dp_helper.c2673 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_dp_dsc_sink_bpp_incr()
2675 u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_bpp_incr()
2710 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], in drm_dp_dsc_sink_max_slice_count()
2713 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_max_slice_count()
2725 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_max_slice_count()
2768 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_dp_dsc_sink_line_buf_depth()
2770 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_line_buf_depth()
2814 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], in drm_dp_dsc_sink_supported_input_bpcs()
2818 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_supported_input_bpcs()
2820 if (!drm_dp_sink_supports_dsc(dsc_dpcd)) in drm_dp_dsc_sink_supported_input_bpcs()

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