| /drivers/gpu/drm/msm/disp/mdp5/ |
| A D | mdp5_cfg.c | 81 .dspp = {
164 .dspp = {
245 .dspp = {
344 .dspp = {
426 .dspp = {
506 .dspp = {
596 .dspp = {
702 .dspp = {
812 .dspp = {
899 .dspp = {
[all …]
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| A D | mdp5_cfg.h | 37 int dspp; member
106 struct mdp5_sub_block dspp; member
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| A D | mdp5_mixer.c | 160 mixer->dspp = lm->dspp; in mdp5_mixer_init()
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| A D | dpu_hw_ctl.c | 144 int dspp; in dpu_hw_ctl_trigger_flush_v1() local
160 for (dspp = DSPP_0; dspp < DSPP_MAX; dspp++) { in dpu_hw_ctl_trigger_flush_v1()
161 if (ctx->pending_dspp_flush_mask[dspp - DSPP_0]) in dpu_hw_ctl_trigger_flush_v1()
163 CTL_DSPP_n_FLUSH(dspp - DSPP_0), in dpu_hw_ctl_trigger_flush_v1()
164 ctx->pending_dspp_flush_mask[dspp - DSPP_0]); in dpu_hw_ctl_trigger_flush_v1()
372 enum dpu_dspp dspp, u32 dspp_sub_blk) in dpu_hw_ctl_update_pending_flush_dspp() argument
374 switch (dspp) { in dpu_hw_ctl_update_pending_flush_dspp()
393 struct dpu_hw_ctl *ctx, enum dpu_dspp dspp, u32 dspp_sub_blk) in dpu_hw_ctl_update_pending_flush_dspp_sub_blocks() argument
395 if (dspp >= DSPP_MAX) in dpu_hw_ctl_update_pending_flush_dspp_sub_blocks()
400 ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(4); in dpu_hw_ctl_update_pending_flush_dspp_sub_blocks()
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| A D | dpu_rm.c | 156 const struct dpu_dspp_cfg *dspp = &cat->dspp[i]; in dpu_rm_init() local
158 hw = dpu_hw_dspp_init(dev, dspp, mmio); in dpu_rm_init()
164 rm->dspp_blks[dspp->id - DSPP_0] = &hw->base; in dpu_rm_init()
339 idx = lm_cfg->dspp - DSPP_0; in _dpu_rm_check_lm_and_get_connected_blks()
341 DPU_ERROR("failed to get dspp on lm %d\n", lm_cfg->dspp); in _dpu_rm_check_lm_and_get_connected_blks()
347 lm_cfg->dspp); in _dpu_rm_check_lm_and_get_connected_blks()
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| /drivers/gpu/drm/msm/disp/dpu1/catalog/ |
| A D | dpu_4_0_sdm845.h | 140 .dspp = DSPP_0,
148 .dspp = DSPP_1,
156 .dspp = DSPP_2,
164 .dspp = DSPP_3,
321 .dspp = sdm845_dspp,
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| A D | dpu_4_1_sdm670.h | 75 .dspp = DSPP_0,
83 .dspp = DSPP_1,
140 .dspp = sdm670_dspp,
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| A D | dpu_5_0_sm8150.h | 143 .dspp = DSPP_0,
151 .dspp = DSPP_1,
159 .dspp = DSPP_2,
167 .dspp = DSPP_3,
373 .dspp = sm8150_dspp,
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| A D | dpu_6_0_sm8250.h | 142 .dspp = DSPP_0,
150 .dspp = DSPP_1,
158 .dspp = DSPP_2,
166 .dspp = DSPP_3,
372 .dspp = sm8250_dspp,
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| A D | dpu_7_0_sm8350.h | 142 .dspp = DSPP_0,
150 .dspp = DSPP_1,
158 .dspp = DSPP_2,
166 .dspp = DSPP_3,
384 .dspp = sm8350_dspp,
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| A D | dpu_9_0_sm8550.h | 139 .dspp = DSPP_0,
147 .dspp = DSPP_1,
155 .dspp = DSPP_2,
163 .dspp = DSPP_3,
392 .dspp = sm8550_dspp,
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| A D | dpu_9_1_sar2130p.h | 139 .dspp = DSPP_0,
147 .dspp = DSPP_1,
155 .dspp = DSPP_2,
163 .dspp = DSPP_3,
392 .dspp = sar2130p_dspp,
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| A D | dpu_10_0_sm8650.h | 139 .dspp = DSPP_0,
147 .dspp = DSPP_1,
155 .dspp = DSPP_2,
163 .dspp = DSPP_3,
435 .dspp = sm8650_dspp,
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| A D | dpu_8_0_sc8280xp.h | 141 .dspp = DSPP_0,
149 .dspp = DSPP_1,
157 .dspp = DSPP_2,
165 .dspp = DSPP_3,
415 .dspp = sc8280xp_dspp,
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| A D | dpu_8_1_sm8450.h | 142 .dspp = DSPP_0,
150 .dspp = DSPP_1,
158 .dspp = DSPP_2,
166 .dspp = DSPP_3,
397 .dspp = sm8450_dspp,
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| A D | dpu_5_1_sc8180x.h | 143 .dspp = DSPP_0,
151 .dspp = DSPP_1,
159 .dspp = DSPP_2,
167 .dspp = DSPP_3,
397 .dspp = sc8180x_dspp,
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| A D | dpu_9_2_x1e80100.h | 138 .dspp = DSPP_0,
146 .dspp = DSPP_1,
154 .dspp = DSPP_2,
162 .dspp = DSPP_3,
433 .dspp = x1e80100_dspp,
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| A D | dpu_8_4_sa8775p.h | 141 .dspp = DSPP_0,
149 .dspp = DSPP_1,
157 .dspp = DSPP_2,
165 .dspp = DSPP_3,
437 .dspp = sa8775p_dspp,
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| A D | dpu_5_4_sm6125.h | 95 .dspp = DSPP_0,
102 .dspp = 0,
213 .dspp = sm6125_dspp,
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| A D | dpu_6_4_sm6350.h | 98 .dspp = DSPP_0,
106 .dspp = 0,
223 .dspp = sm6350_dspp,
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| A D | dpu_12_0_sm8750.h | 140 .dspp = DSPP_0,
148 .dspp = DSPP_1,
156 .dspp = DSPP_2,
164 .dspp = DSPP_3,
476 .dspp = sm8750_dspp,
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| A D | dpu_6_5_qcm2290.h | 62 .dspp = DSPP_0,
135 .dspp = qcm2290_dspp,
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| A D | dpu_3_2_sdm660.h | 113 .dspp = DSPP_0,
121 .dspp = DSPP_1,
270 .dspp = sdm660_dspp,
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| A D | dpu_6_3_sm6115.h | 62 .dspp = DSPP_0,
142 .dspp = sm6115_dspp,
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| A D | dpu_6_9_sm6375.h | 64 .dspp = DSPP_0,
151 .dspp = sm6375_dspp,
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