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Searched refs:dtable (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/renesas/
A Drzg2l-cpg.h106 const struct clk_div_table *dtable; member
163 .parent = _parent, .dtable = _dtable, \
167 .parent = _parent, .dtable = _dtable, \
172 .parent = _parent, .dtable = _dtable, \
A Dr9a09g077-cpg.c62 .parent = _parent, .dtable = _dtable, .flag = 0)
179 if (core->dtable) in r9a09g077_cpg_div_clk_register()
186 core->dtable, in r9a09g077_cpg_div_clk_register()
A Drzv2h-cpg.h176 const struct clk_div_table *dtable; member
210 .dtable = _dtable, \
A Drzg2l-cpg.c115 const struct clk_div_table *dtable; member
307 return divider_recalc_rate(hw, parent_rate, val, div_hw_data->dtable, in rzg3s_div_clk_recalc_rate()
319 return divider_determine_rate(hw, req, div_hw_data->dtable, div_hw_data->width, in rzg3s_div_clk_determine_rate()
335 val = divider_get_val(rate, parent_rate, div_hw_data->dtable, div_hw_data->width, in rzg3s_div_clk_set_rate()
382 for (clkt = core->dtable; clkt->div; clkt++) { in rzg3s_cpg_div_clk_register()
390 div_hw_data->dtable = core->dtable; in rzg3s_cpg_div_clk_register()
428 if (core->dtable) in rzg2l_cpg_div_clk_register()
435 core->dtable, in rzg2l_cpg_div_clk_register()
A Drenesas-cpg-mssr.h34 const struct clk_div_table *dtable; member
A Drzv2h-cpg.c413 div->table = core->dtable; in rzv2h_cpg_ddiv_clk_register()

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