Searched refs:dtable_1_32 (Results 1 – 3 of 3) sorted by relevance
| /drivers/clk/renesas/ |
| A D | r9a07g043-cpg.c | 81 static const struct clk_div_table dtable_1_32[] = { variable
122 DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
134 DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32),
137 DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32),
139 DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
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| A D | r9a08g045-cpg.c | 114 static const struct clk_div_table dtable_1_32[] = { variable
164 dtable_1_32, 0, 0, 0, NULL),
179 dtable_1_32, 0, 0, 0, NULL),
182 dtable_1_32, 0, 0, 0, NULL),
184 dtable_1_32, 0, 0, 0, NULL),
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| A D | r9a07g044-cpg.c | 88 static const struct clk_div_table dtable_1_32[] = { variable
190 DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
203 DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32),
206 DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32),
208 DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
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