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Searched refs:dummy_pstate_latency_us (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c168 .dummy_pstate_latency_us = 5,
413 dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us; in dcn30_fpu_calculate_wm_and_dlg()
434 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn30_fpu_calculate_wm_and_dlg()
633 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn30_find_dummy_latency_index_for_fw_based_mclk_switch()
701 base->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38; in dcn3_fpu_build_wm_range_table()
703 base->bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; in dcn3_fpu_build_wm_range_table()
705 base->bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; in dcn3_fpu_build_wm_range_table()
707 base->bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; in dcn3_fpu_build_wm_range_table()
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c247 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50; in dcn32_build_wm_range_table_fpu()
249 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; in dcn32_build_wm_range_table_fpu()
251 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; in dcn32_build_wm_range_table_fpu()
253 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; in dcn32_build_wm_range_table_fpu()
292 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
2344 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()
2513 dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()
2534 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()
2619 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()
3096 if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000) in dcn32_update_bw_bounding_box_fpu()
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/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h256 unsigned int dummy_pstate_latency_us; member
/drivers/gpu/drm/amd/display/dc/dml/dcn302/
A Ddcn302_fpu.c156 .dummy_pstate_latency_us = 5,
/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_structs.h236 double dummy_pstate_latency_us; member
A Ddisplay_mode_vba.c359 mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us; in fetch_socbb_params()
/drivers/gpu/drm/amd/display/dc/dml/dcn303/
A Ddcn303_fpu.c155 .dummy_pstate_latency_us = 5,
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddcn31_fpu.c296 .dummy_pstate_latency_us = 10.0
472 …ext->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; in dcn315_update_soc_for_wm_a()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c324 .dummy_pstate_latency_us = 5.0,
435 .dummy_pstate_latency_us = 5.0,
2021 if ((int)(bb->dummy_pstate_latency_us * 1000) in dcn20_patch_bounding_box()
2024 bb->dummy_pstate_latency_us = in dcn20_patch_bounding_box()
2105 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || in dcn20_validate_bandwidth_fp()
2112 …ext->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; in dcn20_validate_bandwidth_fp()
/drivers/gpu/drm/amd/display/dc/dml/dcn321/
A Ddcn321_fpu.c654 if ((int)(dcn3_21_soc.dummy_pstate_latency_us * 1000) in dcn321_update_bw_bounding_box_fpu()
657 dcn3_21_soc.dummy_pstate_latency_us = in dcn321_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_wrapper.c197 …te_array[j].dram_clock_change_latency_us = s_global->dummy_pstate_table[i].dummy_pstate_latency_us; in calculate_lowest_supported_state_for_temp_read()

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