Searched refs:dummy_pstate_table (Results 1 – 5 of 5) sorted by relevance
413 dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us; in dcn30_fpu_calculate_wm_and_dlg()429 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts) in dcn30_fpu_calculate_wm_and_dlg()434 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn30_fpu_calculate_wm_and_dlg()700 base->bw_params->dummy_pstate_table[0].dram_speed_mts = 1600; in dcn3_fpu_build_wm_range_table()701 base->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38; in dcn3_fpu_build_wm_range_table()702 base->bw_params->dummy_pstate_table[1].dram_speed_mts = 8000; in dcn3_fpu_build_wm_range_table()703 base->bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; in dcn3_fpu_build_wm_range_table()704 base->bw_params->dummy_pstate_table[2].dram_speed_mts = 10000; in dcn3_fpu_build_wm_range_table()705 base->bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; in dcn3_fpu_build_wm_range_table()706 base->bw_params->dummy_pstate_table[3].dram_speed_mts = 16000; in dcn3_fpu_build_wm_range_table()[all …]
92 struct dummy_pstate_entry dummy_pstate_table[4]; member
197 …ctx.states.state_array[j].dram_clock_change_latency_us = s_global->dummy_pstate_table[i].dummy_pst… in calculate_lowest_supported_state_for_temp_read()214 …dml_core_ctx.states.state_array[result].dram_speed_mts < s_global->dummy_pstate_table[i].dram_spee… in calculate_lowest_supported_state_for_temp_read()433 copy_dummy_pstate_table(s->dummy_pstate_table, in_dc->clk_mgr->bw_params->dummy_pstate_table, 4); in dml2_validate_and_build_resource()
247 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50; in dcn32_build_wm_range_table_fpu()249 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; in dcn32_build_wm_range_table_fpu()251 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; in dcn32_build_wm_range_table_fpu()253 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; in dcn32_build_wm_range_table_fpu()292 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()2344 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()2392 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()2513 dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()2529 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts) in dcn32_calculate_wm_and_dlg_fpu()2534 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()[all …]
268 struct dummy_pstate_entry dummy_pstate_table[4]; member
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