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Searched refs:dwb_pipe_inst (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_hwseq.c434 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); in dcn30_set_writeback()
443 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); in dcn30_set_writeback()
455 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_update_writeback()
457 __func__, wb_info->dwb_pipe_inst,\ in dcn30_update_writeback()
531 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_enable_writeback()
535 __func__, wb_info->dwb_pipe_inst,\ in dcn30_enable_writeback()
552 unsigned int dwb_pipe_inst) in dcn30_disable_writeback() argument
557 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); in dcn30_disable_writeback()
558 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dcn30_disable_writeback()
559 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; in dcn30_disable_writeback()
[all …]
A Ddcn30_hwseq.h48 unsigned int dwb_pipe_inst);
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_stream.c487 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { in dc_stream_add_writeback()
496 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
504 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) { in dc_stream_add_writeback()
545 uint32_t dwb_pipe_inst) in dc_stream_fc_disable_writeback() argument
547 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_fc_disable_writeback()
554 if (dwb_pipe_inst >= MAX_DWB_PIPES) { in dc_stream_fc_disable_writeback()
582 uint32_t dwb_pipe_inst) in dc_stream_remove_writeback() argument
590 if (dwb_pipe_inst >= MAX_DWB_PIPES) { in dc_stream_remove_writeback()
604 if (stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) in dc_stream_remove_writeback()
627 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_remove_writeback()
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/drivers/gpu/drm/amd/display/dc/
A Ddc_stream.h99 int dwb_pipe_inst; member
442 uint32_t dwb_pipe_inst);
446 uint32_t dwb_pipe_inst);
/drivers/gpu/drm/amd/display/dc/optc/dcn20/
A Ddcn20_optc.c244 uint32_t dwb_pipe_inst) in optc2_set_dwb_source() argument
248 if (dwb_pipe_inst == 0) in optc2_set_dwb_source()
251 else if (dwb_pipe_inst == 1) in optc2_set_dwb_source()
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.h120 unsigned int dwb_pipe_inst);
A Ddcn20_hwseq.c2540 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); in dcn20_enable_writeback()
2542 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn20_enable_writeback()
2543 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn20_enable_writeback()
2547 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); in dcn20_enable_writeback()
2550 …config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); in dcn20_enable_writeback()
2560 unsigned int dwb_pipe_inst) in dcn20_disable_writeback() argument
2565 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); in dcn20_disable_writeback()
2566 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dcn20_disable_writeback()
2567 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; in dcn20_disable_writeback()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dtiming_generator.h307 uint32_t dwb_pipe_inst);
/drivers/gpu/drm/amd/display/dc/hwss/
A Dhw_sequencer.h337 unsigned int dwb_pipe_inst);
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm.c10033 wb_info->dwb_pipe_inst = 0; in dm_set_writeback()

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