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Searched refs:ecc_cfg (Results 1 – 4 of 4) sorted by relevance

/drivers/spi/
A Dspi-qpic-snand.c256 ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL); in qcom_spi_ecc_init_ctx_pipelined()
257 if (!ecc_cfg) in qcom_spi_ecc_init_ctx_pipelined()
314 ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size; in qcom_spi_ecc_init_ctx_pipelined()
318 ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes; in qcom_spi_ecc_init_ctx_pipelined()
387 ecc_cfg->strength, ecc_cfg->step_size); in qcom_spi_ecc_init_ctx_pipelined()
392 kfree(ecc_cfg); in qcom_spi_ecc_init_ctx_pipelined()
400 kfree(ecc_cfg); in qcom_spi_ecc_cleanup_ctx_pipelined()
755 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; in qcom_spi_read_cw_raw()
870 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; in qcom_spi_read_page_ecc()
961 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; in qcom_spi_read_page_oob()
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A Dspi-mtk-snfi.c311 struct mtk_ecc_config *ecc_cfg; member
671 struct mtk_ecc_config *ecc_cfg; in mtk_snand_ecc_init_ctx() local
678 ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL); in mtk_snand_ecc_init_ctx()
679 if (!ecc_cfg) in mtk_snand_ecc_init_ctx()
682 nand->ecc.ctx.priv = ecc_cfg; in mtk_snand_ecc_init_ctx()
699 ecc_cfg->mode = ECC_NFI_MODE; in mtk_snand_ecc_init_ctx()
743 kfree(ecc_cfg); in mtk_snand_ecc_cleanup_ctx()
758 snf->ecc_cfg = ecc_cfg; in mtk_snand_ecc_prepare_io_req()
768 snf->ecc_cfg = NULL; in mtk_snand_ecc_finish_io_req()
944 snf->ecc_cfg->op = ECC_DECODE; in mtk_snand_read_page_cache()
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/drivers/mtd/nand/raw/
A Dpl35x-nand-controller.c121 u32 ecc_cfg; member
276 u32 ecc_cfg; in pl35x_smc_set_ecc_mode() local
278 ecc_cfg = readl(nfc->conf_regs + PL35X_SMC_ECC_CFG); in pl35x_smc_set_ecc_mode()
279 ecc_cfg &= ~PL35X_SMC_ECC_CFG_MODE_MASK; in pl35x_smc_set_ecc_mode()
280 ecc_cfg |= mode; in pl35x_smc_set_ecc_mode()
281 writel(ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG); in pl35x_smc_set_ecc_mode()
285 plnand->ecc_cfg = ecc_cfg; in pl35x_smc_set_ecc_mode()
326 writel(plnand->ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG); in pl35x_nand_select_target()
890 plnand->ecc_cfg = readl(nfc->conf_regs + PL35X_SMC_ECC_CFG); in pl35x_smc_set_ecc_pg_size()
891 plnand->ecc_cfg &= ~PL35X_SMC_ECC_CFG_PGSIZE_MASK; in pl35x_smc_set_ecc_pg_size()
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A Dmtk_nand.c144 struct mtk_ecc_config ecc_cfg; member
383 nfc->ecc_cfg.strength = chip->ecc.strength; in mtk_nfc_hw_runtime_config()
647 nfc->ecc_cfg.mode = ECC_DMA_MODE; in mtk_nfc_sector_encode()
648 nfc->ecc_cfg.op = ECC_ENCODE; in mtk_nfc_sector_encode()
843 nfc->ecc_cfg.op = ECC_ENCODE; in mtk_nfc_write_page()
844 nfc->ecc_cfg.mode = ECC_NFI_MODE; in mtk_nfc_write_page()
845 ret = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg); in mtk_nfc_write_page()
979 nfc->ecc_cfg.mode = ECC_NFI_MODE; in mtk_nfc_read_subpage()
980 nfc->ecc_cfg.sectors = sectors; in mtk_nfc_read_subpage()
981 nfc->ecc_cfg.op = ECC_DECODE; in mtk_nfc_read_subpage()
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