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Searched refs:edp (Results 1 – 16 of 16) sorted by relevance

/drivers/phy/qualcomm/
A Dphy-qcom-edp.c229 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
241 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
251 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_init()
382 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_on_v4()
383 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_power_on_v4()
567 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_on_v6()
793 writel(0x01, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
1077 edp->is_edp = edp->cfg->is_edp; in qcom_edp_phy_probe()
1080 if (IS_ERR(edp->edp)) in qcom_edp_phy_probe()
1081 return PTR_ERR(edp->edp); in qcom_edp_phy_probe()
[all …]
A DMakefile4 obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o
/drivers/gpu/drm/gma500/
A Dintel_bios.c48 struct bdb_edp *edp; in parse_edp() local
55 dev_priv->edp.bpp = 18; in parse_edp()
56 if (!edp) { in parse_edp()
67 dev_priv->edp.bpp = 18; in parse_edp()
70 dev_priv->edp.bpp = 24; in parse_edp()
73 dev_priv->edp.bpp = 30; in parse_edp()
84 dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8, in parse_edp()
85 dev_priv->edp.pps.t9, dev_priv->edp.pps.t10, in parse_edp()
92 dev_priv->edp.lanes = 1; in parse_edp()
103 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); in parse_edp()
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A Dcdv_intel_dp.c1139 if (edp) { in cdv_intel_dp_prepare()
1147 if (edp) in cdv_intel_dp_prepare()
1156 if (edp) in cdv_intel_dp_commit()
1160 if (edp) in cdv_intel_dp_commit()
1174 if (edp) { in cdv_intel_dp_dpms()
1192 if (edp) in cdv_intel_dp_dpms()
1699 if (edp) in cdv_intel_dp_detect()
1703 if (edp) in cdv_intel_dp_detect()
1717 if (edp) in cdv_intel_dp_detect()
1787 if (edp) in cdv_intel_dp_detect_audio()
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A Dpsb_drv.h535 } edp; member
A Dcdv_intel_display.c688 switch (dev_priv->edp.bpp) { in cdv_intel_crtc_mode_set()
/drivers/gpu/drm/i915/display/
A Dintel_dp_aux_backlight.c157 panel->backlight.edp.intel_cap.sdr_uses_aux = in intel_dp_aux_supports_hdr_backlight()
161 panel->backlight.edp.intel_cap.supports_2020_gamut = in intel_dp_aux_supports_hdr_backlight()
248 panel->backlight.edp.intel_cap.sdr_uses_aux) { in intel_dp_aux_hdr_set_backlight()
339 panel->backlight.edp.intel_cap.sdr_uses_aux) { in intel_dp_aux_hdr_enable_backlight()
372 if (panel->backlight.edp.intel_cap.sdr_uses_aux) in intel_dp_aux_hdr_disable_backlight()
485 if (!panel->backlight.edp.vesa.info.aux_set) { in intel_dp_aux_vesa_set_backlight()
502 if (!panel->backlight.edp.vesa.info.aux_enable) { in intel_dp_aux_vesa_enable_backlight()
505 if (!panel->backlight.edp.vesa.info.aux_set) in intel_dp_aux_vesa_enable_backlight()
529 if (!panel->backlight.edp.vesa.info.aux_enable) in intel_dp_aux_vesa_disable_backlight()
562 if (!panel->backlight.edp.vesa.info.aux_set || in intel_dp_aux_vesa_setup_backlight()
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A Dintel_bios.c1421 const struct bdb_edp *edp; in parse_edp() local
1426 if (!edp) in parse_edp()
1431 panel->vbt.edp.bpp = 18; in parse_edp()
1434 panel->vbt.edp.bpp = 24; in parse_edp()
1437 panel->vbt.edp.bpp = 30; in parse_edp()
1448 panel->vbt.edp.rate = in parse_edp()
1471 panel->vbt.edp.lanes = 1; in parse_edp()
1474 panel->vbt.edp.lanes = 2; in parse_edp()
1477 panel->vbt.edp.lanes = 4; in parse_edp()
1531 panel->vbt.edp.low_vswing = in parse_edp()
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A Dintel_dp.c547 int edp_max_rate = connector->panel.vbt.edp.max_link_rate; in vbt_max_link_rate()
1405 connector->panel.vbt.edp.dsc_disable) in intel_dp_has_dsc()
1731 connector->panel.vbt.edp.bpp && in intel_dp_max_bpp()
1732 connector->panel.vbt.edp.bpp < bpp) { in intel_dp_max_bpp()
1735 connector->panel.vbt.edp.bpp); in intel_dp_max_bpp()
1736 bpp = connector->panel.vbt.edp.bpp; in intel_dp_max_bpp()
2997 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay; in intel_dp_drrs_compute_config()
4220 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) { in intel_edp_fixup_vbt_bpp()
4236 pipe_bpp, connector->panel.vbt.edp.bpp); in intel_edp_fixup_vbt_bpp()
4237 connector->panel.vbt.edp.bpp = pipe_bpp; in intel_edp_fixup_vbt_bpp()
A Dintel_ddi_buf_trans.c1128 return connector->panel.vbt.edp.hobl && !intel_dp->hobl_failed; in use_edp_hobl()
1136 return connector->panel.vbt.edp.low_vswing; in use_edp_low_vswing()
A Dintel_display_types.h350 } edp; member
432 } edp; member
A Dintel_pps.c1489 *vbt = connector->panel.vbt.edp.pps; in pps_init_delays_vbt()
/drivers/gpu/drm/tegra/
A Ddp.h138 unsigned char edp; member
A Ddp.c48 link->edp = 0; in drm_dp_link_reset()
201 link->edp = drm_dp_edp_revisions[value]; in drm_dp_link_probe()
236 if (link->edp >= 0x14) { in drm_dp_link_probe()
A Dsor.c925 if (link->edp == 0) in tegra_sor_dp_link_configure()
/drivers/gpu/drm/panel/
A DMakefile15 obj-$(CONFIG_DRM_PANEL_EDP) += panel-edp.o

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