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/drivers/net/ethernet/mellanox/mlx5/core/
A DMakefile25 mlx5_core-$(CONFIG_MLX5_CORE_EN) += en/rqt.o en/tir.o en/rss.o en/rx_res.o \
28 en_selftest.o en/port.o en/monitor_stats.o en/health.o \
29 en/reporter_tx.o en/reporter_rx.o en/params.o en/xsk/pool.o \
30 en/xsk/setup.o en/xsk/rx.o en/xsk/tx.o en/devlink.o en/ptp.o \
31 en/qos.o en/htb.o en/trap.o en/fs_tt_redirect.o en/selq.o \
47 en/tc_tun_vxlan.o en/tc_tun_gre.o en/tc_tun_geneve.o \
49 en/tc/post_act.o en/tc/int_port.o en/tc/meter.o \
53 en/tc/act/accept.o en/tc/act/mark.o en/tc/act/goto.o \
54 en/tc/act/tun.o en/tc/act/csum.o en/tc/act/pedit.o \
55 en/tc/act/vlan.o en/tc/act/vlan_mangle.o en/tc/act/mpls.o \
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dce60/
A Dhw_translate_dce60.c67 uint32_t *en) in offset_to_id() argument
105 *en = GPIO_HPD_1; in offset_to_id()
108 *en = GPIO_HPD_2; in offset_to_id()
111 *en = GPIO_HPD_3; in offset_to_id()
212 uint32_t en, in id_to_offset() argument
220 switch (en) { in id_to_offset()
252 switch (en) { in id_to_offset()
284 switch (en) { in id_to_offset()
313 switch (en) { in id_to_offset()
338 switch (en) { in id_to_offset()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dce80/
A Dhw_translate_dce80.c67 uint32_t *en) in offset_to_id() argument
105 *en = GPIO_HPD_1; in offset_to_id()
108 *en = GPIO_HPD_2; in offset_to_id()
111 *en = GPIO_HPD_3; in offset_to_id()
212 uint32_t en, in id_to_offset() argument
220 switch (en) { in id_to_offset()
252 switch (en) { in id_to_offset()
284 switch (en) { in id_to_offset()
313 switch (en) { in id_to_offset()
338 switch (en) { in id_to_offset()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dce110/
A Dhw_translate_dce110.c43 uint32_t *en) in offset_to_id() argument
81 *en = GPIO_HPD_1; in offset_to_id()
84 *en = GPIO_HPD_2; in offset_to_id()
87 *en = GPIO_HPD_3; in offset_to_id()
183 uint32_t en, in id_to_offset() argument
191 switch (en) { in id_to_offset()
223 switch (en) { in id_to_offset()
255 switch (en) { in id_to_offset()
284 switch (en) { in id_to_offset()
309 switch (en) { in id_to_offset()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dce120/
A Dhw_translate_dce120.c65 uint32_t *en) in offset_to_id() argument
103 *en = GPIO_HPD_1; in offset_to_id()
106 *en = GPIO_HPD_2; in offset_to_id()
109 *en = GPIO_HPD_3; in offset_to_id()
205 uint32_t en, in id_to_offset() argument
213 switch (en) { in id_to_offset()
245 switch (en) { in id_to_offset()
277 switch (en) { in id_to_offset()
306 switch (en) { in id_to_offset()
331 switch (en) { in id_to_offset()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
A Dhw_translate_dcn10.c65 uint32_t *en) in offset_to_id() argument
103 *en = GPIO_HPD_1; in offset_to_id()
106 *en = GPIO_HPD_2; in offset_to_id()
109 *en = GPIO_HPD_3; in offset_to_id()
205 uint32_t en, in id_to_offset() argument
213 switch (en) { in id_to_offset()
245 switch (en) { in id_to_offset()
277 switch (en) { in id_to_offset()
306 switch (en) { in id_to_offset()
331 switch (en) { in id_to_offset()
[all …]
A Dhw_factory_dcn10.c155 generic->regs = &generic_regs[en]; in define_generic_registers()
156 generic->shifts = &generic_shift[en]; in define_generic_registers()
157 generic->masks = &generic_mask[en]; in define_generic_registers()
158 generic->base.regs = &generic_regs[en].gpio; in define_generic_registers()
163 uint32_t en) in define_ddc_registers() argument
169 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
170 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
173 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
174 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
190 hpd->regs = &hpd_regs[en]; in define_hpd_registers()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
A Dhw_translate_dcn20.c69 uint32_t *en) in offset_to_id() argument
107 *en = GPIO_HPD_1; in offset_to_id()
110 *en = GPIO_HPD_2; in offset_to_id()
113 *en = GPIO_HPD_3; in offset_to_id()
116 *en = GPIO_HPD_4; in offset_to_id()
194 uint32_t en, in id_to_offset() argument
202 switch (en) { in id_to_offset()
232 switch (en) { in id_to_offset()
262 switch (en) { in id_to_offset()
291 switch (en) { in id_to_offset()
[all …]
A Dhw_factory_dcn20.c183 uint32_t en) in define_ddc_registers() argument
189 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
193 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
201 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
202 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
210 hpd->regs = &hpd_regs[en]; in define_hpd_registers()
213 hpd->base.regs = &hpd_regs[en].gpio; in define_hpd_registers()
220 generic->regs = &generic_regs[en]; in define_generic_registers()
221 generic->shifts = &generic_shift[en]; in define_generic_registers()
222 generic->masks = &generic_mask[en]; in define_generic_registers()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
A Dhw_translate_dcn30.c74 uint32_t *en) in offset_to_id() argument
112 *en = GPIO_HPD_1; in offset_to_id()
115 *en = GPIO_HPD_2; in offset_to_id()
118 *en = GPIO_HPD_3; in offset_to_id()
121 *en = GPIO_HPD_4; in offset_to_id()
199 uint32_t en, in id_to_offset() argument
207 switch (en) { in id_to_offset()
237 switch (en) { in id_to_offset()
267 switch (en) { in id_to_offset()
296 switch (en) { in id_to_offset()
[all …]
A Dhw_factory_dcn30.c192 generic->regs = &generic_regs[en]; in define_generic_registers()
193 generic->shifts = &generic_shift[en]; in define_generic_registers()
194 generic->masks = &generic_mask[en]; in define_generic_registers()
195 generic->base.regs = &generic_regs[en].gpio; in define_generic_registers()
200 uint32_t en) in define_ddc_registers() argument
206 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
210 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
218 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
219 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
227 hpd->regs = &hpd_regs[en]; in define_hpd_registers()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
A Dhw_translate_dcn21.c68 uint32_t *en) in offset_to_id() argument
106 *en = GPIO_HPD_1; in offset_to_id()
109 *en = GPIO_HPD_2; in offset_to_id()
112 *en = GPIO_HPD_3; in offset_to_id()
115 *en = GPIO_HPD_4; in offset_to_id()
190 uint32_t en, in id_to_offset() argument
198 switch (en) { in id_to_offset()
225 switch (en) { in id_to_offset()
252 switch (en) { in id_to_offset()
281 switch (en) { in id_to_offset()
[all …]
A Dhw_factory_dcn21.c163 generic->regs = &generic_regs[en]; in define_generic_registers()
164 generic->shifts = &generic_shift[en]; in define_generic_registers()
165 generic->masks = &generic_mask[en]; in define_generic_registers()
166 generic->base.regs = &generic_regs[en].gpio; in define_generic_registers()
171 uint32_t en) in define_ddc_registers() argument
177 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
181 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
189 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
190 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
198 hpd->regs = &hpd_regs[en]; in define_hpd_registers()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
A Dhw_translate_dcn315.c69 uint32_t *en) in offset_to_id() argument
107 *en = GPIO_HPD_1; in offset_to_id()
110 *en = GPIO_HPD_2; in offset_to_id()
113 *en = GPIO_HPD_3; in offset_to_id()
116 *en = GPIO_HPD_4; in offset_to_id()
191 uint32_t en, in id_to_offset() argument
199 switch (en) { in id_to_offset()
226 switch (en) { in id_to_offset()
253 switch (en) { in id_to_offset()
282 switch (en) { in id_to_offset()
[all …]
A Dhw_factory_dcn315.c184 generic->regs = &generic_regs[en]; in define_generic_registers()
185 generic->shifts = &generic_shift[en]; in define_generic_registers()
186 generic->masks = &generic_mask[en]; in define_generic_registers()
187 generic->base.regs = &generic_regs[en].gpio; in define_generic_registers()
192 uint32_t en) in define_ddc_registers() argument
198 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
202 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
210 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
211 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
219 hpd->regs = &hpd_regs[en]; in define_hpd_registers()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
A Dhw_translate_dcn32.c67 uint32_t *en) in offset_to_id() argument
102 *en = GPIO_HPD_1; in offset_to_id()
105 *en = GPIO_HPD_2; in offset_to_id()
108 *en = GPIO_HPD_3; in offset_to_id()
111 *en = GPIO_HPD_4; in offset_to_id()
172 uint32_t en, in id_to_offset() argument
180 switch (en) { in id_to_offset()
207 switch (en) { in id_to_offset()
234 switch (en) { in id_to_offset()
260 switch (en) { in id_to_offset()
[all …]
A Dhw_factory_dcn32.c196 generic->regs = &generic_regs[en]; in define_generic_registers()
197 generic->shifts = &generic_shift[en]; in define_generic_registers()
198 generic->masks = &generic_mask[en]; in define_generic_registers()
199 generic->base.regs = &generic_regs[en].gpio; in define_generic_registers()
204 uint32_t en) in define_ddc_registers() argument
210 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
214 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
222 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
223 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
231 hpd->regs = &hpd_regs[en]; in define_hpd_registers()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn401/
A Dhw_translate_dcn401.c42 uint32_t *en) in offset_to_id() argument
77 *en = GPIO_HPD_1; in offset_to_id()
80 *en = GPIO_HPD_2; in offset_to_id()
83 *en = GPIO_HPD_3; in offset_to_id()
86 *en = GPIO_HPD_4; in offset_to_id()
156 uint32_t en, in id_to_offset() argument
164 switch (en) { in id_to_offset()
191 switch (en) { in id_to_offset()
218 switch (en) { in id_to_offset()
244 switch (en) { in id_to_offset()
[all …]
A Dhw_factory_dcn401.c188 generic->regs = &generic_regs[en]; in define_generic_registers()
189 generic->shifts = &generic_shift[en]; in define_generic_registers()
190 generic->masks = &generic_mask[en]; in define_generic_registers()
191 generic->base.regs = &generic_regs[en].gpio; in define_generic_registers()
196 uint32_t en) in define_ddc_registers() argument
202 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
206 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
214 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
215 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
223 hpd->regs = &hpd_regs[en]; in define_hpd_registers()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/
A Dgpio_service.c132 uint32_t en; in dal_gpio_service_create_irq() local
148 uint32_t en; in dal_gpio_service_create_generic_mux() local
179 uint32_t en) in dal_gpio_get_generic_pin_info() argument
240 uint32_t en) in is_pin_busy() argument
251 uint32_t en) in set_pin_busy() argument
262 uint32_t en) in set_pin_free() argument
273 uint32_t en) in dal_gpio_service_lock() argument
287 uint32_t en) in dal_gpio_service_unlock() argument
303 uint32_t en = gpio->en; in dal_gpio_service_open() local
451 uint32_t en) in dal_gpio_create_irq() argument
[all …]
A Dgpio_base.c111 return dal_gpio_service_lock(gpio->service, gpio->id, gpio->en); in dal_gpio_lock_pin()
117 return dal_gpio_service_unlock(gpio->service, gpio->id, gpio->en); in dal_gpio_unlock_pin()
141 return gpio->en; in dal_gpio_get_enum()
161 gpio->id, gpio->en, pin_info) ? in dal_gpio_get_pin_info()
170 switch (gpio->en) { in dal_gpio_get_sync_source()
188 switch (gpio->en) { in dal_gpio_get_sync_source()
202 switch (gpio->en) { in dal_gpio_get_sync_source()
212 switch (gpio->en) { in dal_gpio_get_sync_source()
270 uint32_t en, in dal_gpio_create() argument
283 gpio->en = en; in dal_gpio_create()
[all …]
A Dhw_ddc.c95 if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) { in set_config()
97 if (hw_gpio->base.en == GPIO_DDC_LINE_DDC_VGA) { in set_config()
173 if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) { in set_config()
182 if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) { in set_config()
191 if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) { in set_config()
218 uint32_t en, in dal_hw_ddc_construct() argument
221 dal_hw_gpio_construct(&ddc->base, id, en, ctx); in dal_hw_ddc_construct()
229 uint32_t en) in dal_hw_ddc_init() argument
231 if (en > GPIO_DDC_LINE_MAX) { in dal_hw_ddc_init()
242 dal_hw_ddc_construct(*hw_ddc, id, en, ctx); in dal_hw_ddc_init()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dgpio.h42 uint32_t en; member
57 uint32_t en);
61 uint32_t en);
65 uint32_t en);
69 uint32_t en);
73 uint32_t en);
77 uint32_t en);
81 uint32_t en);
88 uint32_t *en);
91 uint32_t en,
/drivers/media/platform/qcom/venus/
A Dhfi_cmds.c457 en->enable = in->enable; in pkt_session_set_property_1x()
520 en->enable = in->enable; in pkt_session_set_property_1x()
529 en->enable = in->enable; in pkt_session_set_property_1x()
572 en->enable = in->enable; in pkt_session_set_property_1x()
579 en->enable = in->enable; in pkt_session_set_property_1x()
586 en->enable = in->enable; in pkt_session_set_property_1x()
593 en->enable = in->enable; in pkt_session_set_property_1x()
853 en->enable = in->enable; in pkt_session_set_property_1x()
869 en->enable = in->enable; in pkt_session_set_property_1x()
876 en->enable = in->enable; in pkt_session_set_property_1x()
[all …]
/drivers/media/pci/ddbridge/
A Dddbridge-ci.c161 memcpy(&ci->en, &en_templ, sizeof(en_templ)); in ci_attach()
162 ci->en.data = ci; in ci_attach()
163 port->en = &ci->en; in ci_attach()
295 ci->en.data = ci; in ci_xo2_attach()
296 port->en = &ci->en; in ci_xo2_attach()
318 cxd_cfg.en = &port->en; in ci_cxd2099_attach()
355 if (!port->en) in ddb_ci_attach()
365 if (port->en) { in ddb_ci_detach()
366 dvb_ca_en50221_release(port->en); in ddb_ci_detach()
373 kfree(port->en->data); in ddb_ci_detach()
[all …]

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