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Searched refs:enable_optc_clock (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/display/dc/optc/dcn301/
A Ddcn301_optc.c141 .enable_optc_clock = optc1_enable_optc_clock,
/drivers/gpu/drm/amd/display/dc/optc/dcn201/
A Ddcn201_optc.c161 .enable_optc_clock = optc1_enable_optc_clock,
/drivers/gpu/drm/amd/display/dc/optc/dcn314/
A Ddcn314_optc.c226 .enable_optc_clock = optc1_enable_optc_clock,
/drivers/gpu/drm/amd/display/dc/optc/dcn32/
A Ddcn32_optc.c331 .enable_optc_clock = optc1_enable_optc_clock,
/drivers/gpu/drm/amd/display/dc/optc/dcn31/
A Ddcn31_optc.c348 .enable_optc_clock = optc1_enable_optc_clock,
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dtiming_generator.h294 void (*enable_optc_clock)(struct timing_generator *tg, bool enable); member
/drivers/gpu/drm/amd/display/dc/optc/dcn30/
A Ddcn30_optc.c389 .enable_optc_clock = optc1_enable_optc_clock,
/drivers/gpu/drm/amd/display/dc/optc/dcn20/
A Ddcn20_optc.c536 .enable_optc_clock = optc1_enable_optc_clock,
/drivers/gpu/drm/amd/display/dc/optc/dcn35/
A Ddcn35_optc.c462 .enable_optc_clock = optc1_enable_optc_clock,
/drivers/gpu/drm/amd/display/dc/optc/dcn401/
A Ddcn401_optc.c493 .enable_optc_clock = optc1_enable_optc_clock,
/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
A Ddcn31_hwseq.c545 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); in dcn31_reset_back_end_for_pipe()
/drivers/gpu/drm/amd/display/dc/optc/dcn10/
A Ddcn10_optc.c1648 .enable_optc_clock = optc1_enable_optc_clock,
/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c799 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); in dcn401_enable_stream_timing()
1836 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); in dcn401_reset_back_end_for_pipe()
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c876 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); in dcn20_enable_stream_timing()
2855 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); in dcn20_reset_back_end_for_pipe()
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c1164 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); in dcn10_enable_stream_timing()
1296 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); in dcn10_reset_back_end_for_pipe()

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