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Searched refs:engine_id (Results 1 – 25 of 118) sorted by relevance

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/drivers/gpu/drm/amd/display/include/
A Dbios_parser_types.h113 enum engine_id engine_id; member
124 enum engine_id engine_id; member
136 enum engine_id engine_id; member
148 enum engine_id engine_id; member
156 enum engine_id hpo_engine_id; /* used for DCN3 */
A Dgrph_object_id.h177 enum engine_id { enum
295 static inline enum engine_id dal_graphics_object_id_get_engine_id( in dal_graphics_object_id_get_engine_id()
299 return (enum engine_id) id.id; in dal_graphics_object_id_get_engine_id()
A Daudio_types.h106 enum engine_id engine_id; member
/drivers/gpu/drm/nouveau/nvkm/falcon/
A Dga100.c38 FLCN_DBG(falcon, "brom: %08x %08x", fw->engine_id, fw->ucode_id); in ga100_flcn_fw_signature()
41 if (fw->engine_id & 0x00000001) { in ga100_flcn_fw_signature()
44 if (fw->engine_id & 0x00000004) { in ga100_flcn_fw_signature()
47 if (fw->engine_id & 0x00000400) { in ga100_flcn_fw_signature()
/drivers/gpu/drm/amd/display/dc/bios/
A Dcommand_table_helper_struct.h40 bool (*engine_bp_to_atom)(enum engine_id engine_id,
57 uint8_t (*dig_encoder_sel_to_atom)(enum engine_id engine_id);
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_link_enc_cfg.c70 enum engine_id eng_id) in get_stream_using_link_enc()
90 enum engine_id eng_id) in remove_link_enc_assignment()
125 enum engine_id eng_id) in add_link_enc_assignment()
158 static enum engine_id find_first_avail_link_enc( in find_first_avail_link_enc()
161 enum engine_id eng_id_requested) in find_first_avail_link_enc()
163 enum engine_id eng_id = ENGINE_ID_UNKNOWN; in find_first_avail_link_enc()
440 enum engine_id eng_id = ENGINE_ID_UNKNOWN; in link_enc_cfg_link_enc_unassign()
453 enum engine_id eng_id = link_enc->preferred_engine; in link_enc_cfg_is_transmitter_mappable()
464 enum engine_id eng_id) in link_enc_cfg_get_stream_using_link_enc()
483 enum engine_id eng_id) in link_enc_cfg_get_link_using_link_enc()
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/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_i2c_hw.c353 DC_I2C_DDC_SELECT, dce_i2c_hw->engine_id); in setup_engine()
668 uint32_t engine_id, in dce_i2c_hw_construct() argument
674 dce_i2c_hw->engine_id = engine_id; in dce_i2c_hw_construct()
691 uint32_t engine_id, in dce100_i2c_hw_construct() argument
698 engine_id, in dce100_i2c_hw_construct()
708 uint32_t engine_id, in dce112_i2c_hw_construct() argument
715 engine_id, in dce112_i2c_hw_construct()
725 uint32_t engine_id, in dcn1_i2c_hw_construct() argument
732 engine_id, in dcn1_i2c_hw_construct()
742 uint32_t engine_id, in dcn2_i2c_hw_construct() argument
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A Ddce_i2c_hw.h294 uint32_t engine_id; member
308 uint32_t engine_id,
316 uint32_t engine_id,
324 uint32_t engine_id,
332 uint32_t engine_id,
340 uint32_t engine_id,
A Ddce_link_encoder.c239 enum engine_id result; in dce110_get_dig_frontend()
574 enum engine_id engine) in get_frontend_source()
965 cntl.engine_id = ENGINE_ID_UNKNOWN; in dce110_link_encoder_hw_init()
1060 cntl.engine_id = enc->preferred_engine; in dce110_link_encoder_enable_tmds_output()
1096 cntl.engine_id = enc->preferred_engine; in dce110_link_encoder_enable_lvds_output()
1134 cntl.engine_id = enc->preferred_engine; in dce110_link_encoder_enable_dp_output()
1173 cntl.engine_id = ENGINE_ID_UNKNOWN; in dce110_link_encoder_enable_dp_mst_output()
1213 cntl.engine_id = enc->preferred_engine; in dce60_link_encoder_enable_dp_output()
1252 cntl.engine_id = ENGINE_ID_UNKNOWN; in dce60_link_encoder_enable_dp_mst_output()
1622 enum engine_id engine, in dce110_link_encoder_connect_dig_be_to_fe()
/drivers/gpu/drm/amd/display/dc/inc/
A Dlink_enc_cfg.h84 enum engine_id eng_id);
89 enum engine_id eng_id);
108 bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct dc_link *link);
A Dcore_types.h73 enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index);
83 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id);
511 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS];
682 enum engine_id digfe_inst;
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_amdkfd_arcturus.c68 unsigned int engine_id, in get_sdma_rlc_reg_offset() argument
74 switch (engine_id) { in get_sdma_rlc_reg_offset()
78 engine_id); in get_sdma_rlc_reg_offset()
117 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, in get_sdma_rlc_reg_offset()
193 uint32_t engine_id, uint32_t queue_id, in kgd_arcturus_hqd_sdma_dump() argument
197 engine_id, queue_id); in kgd_arcturus_hqd_sdma_dump()
A Damdgpu_amdkfd_gfx_v12.c77 unsigned int engine_id, in get_sdma_rlc_reg_offset() argument
83 switch (engine_id) { in get_sdma_rlc_reg_offset()
99 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, in get_sdma_rlc_reg_offset()
137 uint32_t engine_id, uint32_t queue_id, in hqd_sdma_dump_v12() argument
141 engine_id, queue_id); in hqd_sdma_dump_v12()
A Damdgpu_amdkfd_gfx_v10_3.c130 unsigned int engine_id, in get_sdma_rlc_reg_offset() argument
136 switch (engine_id) { in get_sdma_rlc_reg_offset()
140 engine_id); in get_sdma_rlc_reg_offset()
163 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, in get_sdma_rlc_reg_offset()
429 uint32_t engine_id, uint32_t queue_id, in hqd_sdma_dump_v10_3() argument
433 engine_id, queue_id); in hqd_sdma_dump_v10_3()
A Damdgpu_amdkfd_gc_9_4_3.c44 unsigned int engine_id, in get_sdma_rlc_reg_offset() argument
48 SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id), in get_sdma_rlc_reg_offset()
54 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, in get_sdma_rlc_reg_offset()
129 uint32_t engine_id, uint32_t queue_id, in kgd_gfx_v9_4_3_hqd_sdma_dump() argument
133 engine_id, queue_id); in kgd_gfx_v9_4_3_hqd_sdma_dump()
A Damdgpu_amdkfd_gfx_v11.c126 unsigned int engine_id, in get_sdma_rlc_reg_offset() argument
132 switch (engine_id) { in get_sdma_rlc_reg_offset()
148 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, in get_sdma_rlc_reg_offset()
414 uint32_t engine_id, uint32_t queue_id, in hqd_sdma_dump_v11() argument
418 engine_id, queue_id); in hqd_sdma_dump_v11()
A Damdgpu_amdkfd_arcturus.h26 uint32_t engine_id, uint32_t queue_id,
/drivers/accel/ivpu/
A Divpu_trace.h33 __field(u32, engine_id)
38 __entry->engine_id = job->engine_idx;
43 __entry->engine_id,
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dlink_encoder.h85 enum engine_id preferred_engine;
144 enum engine_id engine,
191 enum engine_id eng_id;
238 enum engine_id preferred_engine;
/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/
A Dga102.c84 fw->engine_id = meta[1]; in ga102_gsp_booter_ctor()
103 FLCN_DBG(falcon, "brom: %08x %08x", fw->engine_id, fw->ucode_id); in ga102_gsp_fwsec_signature()
106 if (fw->engine_id & 0x00000400) { in ga102_gsp_fwsec_signature()
/drivers/gpu/drm/amd/display/dc/dio/dcn10/
A Ddcn10_link_encoder.c424 enum engine_id engine) in get_frontend_source()
451 enum engine_id result; in dcn10_get_dig_frontend()
836 cntl.engine_id = ENGINE_ID_UNKNOWN; in dcn10_link_encoder_hw_init()
932 cntl.engine_id = enc->preferred_engine; in dcn10_link_encoder_enable_tmds_output()
989 cntl.engine_id = enc->preferred_engine; in dcn10_link_encoder_enable_dp_output()
1028 cntl.engine_id = ENGINE_ID_UNKNOWN; in dcn10_link_encoder_enable_dp_mst_output()
1346 enum engine_id engine, in dcn10_link_encoder_connect_dig_be_to_fe()
/drivers/gpu/drm/amd/display/dc/dio/dcn314/
A Ddcn314_dio_stream_encoder.c116 cntl.engine_id = enc1->base.id; in enc314_stream_encoder_dvi_set_stream_attribute()
157 cntl.engine_id = enc1->base.id; in enc314_stream_encoder_hdmi_set_stream_attribute()
488 enum engine_id eng_id, in dcn314_dio_stream_encoder_construct()
/drivers/gpu/drm/amd/display/dc/dio/dcn35/
A Ddcn35_dio_stream_encoder.c62 cntl.engine_id = enc1->base.id; in enc35_stream_encoder_dvi_set_stream_attribute()
102 cntl.engine_id = enc1->base.id; in enc35_stream_encoder_hdmi_set_stream_attribute()
502 enum engine_id eng_id, in dcn35_dio_stream_encoder_construct()
/drivers/gpu/drm/amd/display/dc/dio/dcn32/
A Ddcn32_dio_stream_encoder.c74 cntl.engine_id = enc1->base.id; in enc32_stream_encoder_dvi_set_stream_attribute()
115 cntl.engine_id = enc1->base.id; in enc32_stream_encoder_hdmi_set_stream_attribute()
475 enum engine_id eng_id, in dcn32_dio_stream_encoder_construct()
/drivers/gpu/drm/nouveau/nvkm/subdev/acr/
A Dga102.c108 .engine_id = lsfw->engine_id, in ga102_acr_wpr_build_lsb()
119 hdr->hs_fmc_params.engid_mask = lsfw->engine_id; in ga102_acr_wpr_build_lsb()

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