Searched refs:ep0_state (Results 1 – 22 of 22) sorted by relevance
612 musb->ep0_state = MUSB_EP0_STAGE_TX; in musb_read_setup()619 musb->ep0_state = MUSB_EP0_STAGE_RX; in musb_read_setup()678 switch (musb->ep0_state) { in musb_g_ep0_irq()697 switch (musb->ep0_state) { in musb_g_ep0_irq()798 switch (musb->ep0_state) { in musb_g_ep0_irq()819 musb->ep0_state = in musb_g_ep0_irq()832 musb->ep0_state = in musb_g_ep0_irq()844 decode_ep0stage(musb->ep0_state)); in musb_g_ep0_irq()932 switch (musb->ep0_state) { in musb_g_ep0_queue()940 musb->ep0_state); in musb_g_ep0_queue()[all …]
407 enum musb_g_ep0_state ep0_state; member
2070 musb->ep0_state = MUSB_EP0_STAGE_SETUP; in musb_g_reset()
391 switch (bdc->ep0_state) { in setup_first_bd_ep0()417 ep0_state_string[bdc->ep0_state]); in setup_first_bd_ep0()877 bdc->ep0_state = WAIT_FOR_SETUP; in ep_set_halt()1419 bdc->ep0_state = WAIT_FOR_DATA_START; in ep0_queue_zlp()1425 bdc->ep0_state = WAIT_FOR_DATA_XMIT; in ep0_queue_zlp()1526 ep0_state_string[bdc->ep0_state]); in bdc_xsf_ep0_data_start()1573 ep0_state_string[bdc->ep0_state]); in bdc_xsf_ep0_status_start()1577 bdc->ep0_state = STATUS_PENDING; in bdc_xsf_ep0_status_start()1613 switch (bdc->ep0_state) { in ep0_xsf_complete()1618 bdc->ep0_state = WAIT_FOR_SETUP; in ep0_xsf_complete()[all …]
430 enum bdc_ep0_state ep0_state; member
221 bdc->ep0_state = WAIT_FOR_SETUP; in bdc_mem_init()
41 switch (mtu->ep0_state) { in decode_ep0_state()150 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in ep0_stall_set()319 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in handle_test_mode()541 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in ep0_rx_state()629 mtu->ep0_state = MU3D_EP0_STATE_TX; in ep0_read_setup()633 mtu->ep0_state = MU3D_EP0_STATE_RX; in ep0_read_setup()715 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in mtu3_ep0_isr()730 switch (mtu->ep0_state) { in mtu3_ep0_isr()753 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in mtu3_ep0_isr()805 switch (mtu->ep0_state) { in ep0_queue()[all …]
343 enum mtu3_g_ep0_state ep0_state; member
639 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in mtu3_state_reset()
722 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in mtu3_link_isr()
177 udc->ep0_state = ISP1760_CTRL_SETUP; in isp1760_udc_ctrl_send_status()224 udc->ep0_state = ISP1760_CTRL_SETUP; in isp1760_udc_ctrl_send_stall()347 udc->ep0_state); in isp1760_ep_rx_ready()388 udc->ep0_state); in isp1760_ep_tx_complete()735 if (udc->ep0_state != ISP1760_CTRL_SETUP) { in isp1760_ep0_setup()743 udc->ep0_state = ISP1760_CTRL_STATUS; in isp1760_ep0_setup()745 udc->ep0_state = ISP1760_CTRL_DATA_IN; in isp1760_ep0_setup()747 udc->ep0_state = ISP1760_CTRL_DATA_OUT; in isp1760_ep0_setup()926 switch (udc->ep0_state) { in isp1760_ep_queue()1046 udc->ep0_state = ISP1760_CTRL_SETUP; in __isp1760_ep_set_halt()[all …]
82 enum isp1760_ctrl_state ep0_state; member
182 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep0_stall()647 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep_init()838 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep0_rx()1269 switch (udc->ep0_state) { in ep0_req_complete()1279 udc->ep0_state = WAIT_FOR_SETUP; in ep0_req_complete()1291 udc->ep0_state = WAIT_FOR_SETUP; in ep0_req_complete()1750 udc->ep0_state = DATA_STATE_XMIT; in __qe_ep_queue()1842 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep_set_halt()2154 udc->ep0_state = WAIT_FOR_SETUP; in reset_irq()2301 udc->ep0_state = WAIT_FOR_SETUP; in fsl_qe_start()[all …]
1039 udc->ep0_state = WAIT_FOR_SETUP; in fsl_ep_set_halt()1268 udc->ep0_state = WAIT_FOR_SETUP; in ep0stall()1285 if (udc->ep0_state != DATA_STATE_XMIT) in ep0_prime_status()1286 udc->ep0_state = WAIT_FOR_OUT_STATUS; in ep0_prime_status()1389 udc->ep0_state = DATA_STATE_XMIT; in ch9getstatus()1507 if (udc->ep0_state == DATA_STATE_XMIT) in setup_received_irq()1519 udc->ep0_state = WAIT_FOR_OUT_STATUS; in setup_received_irq()1537 switch (udc->ep0_state) { in ep0_req_complete()1540 udc->ep0_state = WAIT_FOR_OUT_STATUS; in ep0_req_complete()1548 udc->ep0_state = WAIT_FOR_SETUP; in ep0_req_complete()[all …]
64 enum ep0_state { enum98 enum ep0_state ep0state;
388 enum ep0_state { enum459 enum ep0_state ep0state;
336 u32 ep0_state; /* Endpoint zero state */ member
503 u32 ep0_state; /* Endpoint zero state */ member
256 enum ep0_state { enum303 enum ep0_state state;
1378 switch (hsotg->ep0_state) { in dwc2_gadget_set_ep0_desc_chain()1395 hsotg->ep0_state); in dwc2_gadget_set_ep0_desc_chain()1501 hs->ep0_state == DWC2_EP0_DATA_OUT) in dwc2_hsotg_ep_queue()1946 hsotg->ep0_state = DWC2_EP0_STATUS_IN; in dwc2_hsotg_process_control()1949 hsotg->ep0_state = DWC2_EP0_DATA_IN; in dwc2_hsotg_process_control()1952 hsotg->ep0_state = DWC2_EP0_DATA_OUT; in dwc2_hsotg_process_control()2058 hsotg->ep0_state = DWC2_EP0_SETUP; in dwc2_hsotg_enqueue_setup()2450 hsotg->ep0_state == DWC2_EP0_DATA_OUT) { in dwc2_hsotg_handle_outdone()2520 if (hsotg->ep0_state == DWC2_EP0_SETUP) in dwc2_hsotg_handle_rx()2534 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); in dwc2_hsotg_handle_rx()[all …]
1210 enum dwc2_ep0_state ep0_state; member
91 enum ep0_state { enum126 enum ep0_state state; /* P: lock */919 enum ep0_state state; in ep0_read()
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