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Searched refs:ethsys (Results 1 – 4 of 4) sorted by relevance

/drivers/net/ethernet/mediatek/
A Dmtk_eth_path.c137 ret = regmap_clear_bits(eth->ethsys, ETHSYS_SYSCFG0, in set_mux_gmac2_to_2p5gphy()
169 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in set_mux_gmac1_gmac2_to_sgmii_rgmii()
184 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in set_mux_gmac1_gmac2_to_sgmii_rgmii()
198 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in set_mux_gmac12_to_gephy_sgmii()
215 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in set_mux_gmac12_to_gephy_sgmii()
A Dmtk_eth_soc.c482 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, in mt7621_gmac0_rgmii_adjust()
645 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
648 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); in mtk_mac_config()
659 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
661 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_config()
705 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_finish()
3765 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3770 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
4095 if (eth->ethsys) in mtk_hw_init()
5081 if (IS_ERR(eth->ethsys)) { in mtk_probe()
[all …]
A Dmtk_eth_soc.h1306 struct regmap *ethsys; member
/drivers/clk/mediatek/
A DKconfig54 bool "Clock driver for MediaTek MT2701 ethsys"
57 This driver supports MediaTek MT2701 ethsys clocks.

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