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Searched refs:event_base (Results 1 – 12 of 12) sorted by relevance

/drivers/clocksource/
A Dtimer-qcom.c34 static void __iomem *event_base; variable
42 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_interrupt()
44 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_interrupt()
53 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_set_next_event()
56 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_set_next_event()
58 writel_relaxed(ctrl, event_base + TIMER_CLEAR); in msm_timer_set_next_event()
59 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); in msm_timer_set_next_event()
65 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); in msm_timer_set_next_event()
73 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_shutdown()
75 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_shutdown()
[all …]
/drivers/perf/
A Dthunderx2_pmu.c334 hwc->event_base = (unsigned long)tx2_pmu->base in init_cntr_base_l3c()
350 hwc->event_base = (unsigned long)tx2_pmu->base in init_cntr_base_dmc()
364 hwc->event_base = (unsigned long)tx2_pmu->base; in init_cntr_base_ccpi2()
380 reg_writel(0, hwc->event_base); in uncore_start_event_l3c()
410 reg_writel(0, hwc->event_base); in uncore_start_event_dmc()
451 hwc->event_base + CCPI2_PERF_CTL); in uncore_start_event_ccpi2()
460 reg_writel(0, hwc->event_base + CCPI2_PERF_CTL); in uncore_stop_event_ccpi2()
480 hwc->event_base + CCPI2_COUNTER_SEL); in tx2_uncore_event_update()
481 new = reg_readl(hwc->event_base + CCPI2_COUNTER_DATA_H); in tx2_uncore_event_update()
483 reg_readl(hwc->event_base + CCPI2_COUNTER_DATA_L); in tx2_uncore_event_update()
[all …]
A Darm-ccn.c893 dt_cfg = hw->event_base; in arm_ccn_pmu_xp_dt_config()
947 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp); in arm_ccn_pmu_xp_watchpoint_config()
990 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base); in arm_ccn_pmu_xp_event_config()
1013 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port, in arm_ccn_pmu_node_event_config()
A Driscv_pmu_sbi.c432 cmask, cflags, hwc->event_base, hwc->config, in pmu_sbi_ctr_get_idx()
436 cmask, cflags, hwc->event_base, hwc->config, 0); in pmu_sbi_ctr_get_idx()
440 hwc->event_base, hwc->config); in pmu_sbi_ctr_get_idx()
A Driscv_pmu.c332 hwc->event_base = mapped_event; in riscv_pmu_event_init()
A Dcxl_pmu.c653 hwc->event_base); in cxl_pmu_event_start()
746 hwc->event_base = event_idx; in cxl_pmu_event_add()
A Darm_pmu.c477 hwc->event_base = 0; in __hw_perf_event_init()
A Darm-cci.c1288 hwc->event_base = 0; in __hw_perf_event_init()
/drivers/perf/hisilicon/
A Dhisi_pcie_pmu.c391 hwc->event_base = HISI_PCIE_EXT_CNT; in hisi_pcie_pmu_event_init()
393 hwc->event_base = HISI_PCIE_CNT; in hisi_pcie_pmu_event_init()
415 return hisi_pcie_pmu_readq(pcie_pmu, event->hw.event_base, idx); in hisi_pcie_pmu_read_counter()
551 hisi_pcie_pmu_writeq(pcie_pmu, hwc->event_base, idx, prev_cnt); in hisi_pcie_pmu_start()
A Dhns3_pmu.c1214 return hns3_pmu_readq(hns3_pmu, event->hw.event_base, event->hw.idx); in hns3_pmu_read_counter()
1271 hwc->event_base = HNS3_PMU_REG_EVENT_EXT_COUNTER; in hns3_pmu_event_init()
1273 hwc->event_base = HNS3_PMU_REG_EVENT_COUNTER; in hns3_pmu_event_init()
/drivers/fpga/
A Ddfl-fme-perf.c788 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); in fme_perf_event_destroy()
826 hwc->event_base = evtype; in fme_perf_event_init()
844 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); in fme_perf_event_update()
858 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); in fme_perf_event_start()
/drivers/dma/idxd/
A Dperfmon.c101 hwc->event_base = ioread64(CNTRCFG_REG(idxd, idx)); in perfmon_assign_hw_event()
189 event->hw.event_base = ioread64(PERFMON_TABLE_OFFSET(idxd)); in perfmon_pmu_event_init()

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