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Searched refs:fbc_en (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_wm_types.h55 bool fbc_en; member
A Di9xx_wm.c810 (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) | in g4x_write_wm_values()
1304 intermediate->fbc_en = optimal->fbc_en && active->fbc_en; in g4x_compute_intermediate_wm()
1344 intermediate->fbc_en && intermediate->cxsr); in g4x_compute_intermediate_wm()
1347 intermediate->fbc_en && intermediate->hpll_en); in g4x_compute_intermediate_wm()
1384 wm->fbc_en = true; in g4x_merge_wm()
1396 if (!wm_state->fbc_en) in g4x_merge_wm()
1397 wm->fbc_en = false; in g4x_merge_wm()
1405 wm->fbc_en = false; in g4x_merge_wm()
3668 wm->fbc_en = tmp & DSPFW_FBC_SR_EN; in g4x_read_wm_values()
3778 active->fbc_en = wm->fbc_en; in g4x_wm_get_hw_state()
[all …]
A Dintel_display_trace.h299 __entry->fbc = wm->fbc_en;
A Dintel_display_types.h847 bool fbc_en; member
/drivers/gpu/drm/amd/display/dc/inc/
A Ddce_calcs.h363 bool fbc_en[maximum_number_of_surfaces]; member
/drivers/gpu/drm/amd/display/dc/basics/
A Ddce_calcs.c345 …if ((data->fbc_en[i] == 1 && (dceip->argb_compression_support || data->d0_underlay_mode != bw_def_… in calculate_bandwidth()
353 if (data->fbc_en[i] == 1) { in calculate_bandwidth()
587 …if (data->enable[i] && data->fbc_en[i] == 1 && (bw_equ(data->rotation_angle[i], bw_int_to_fixed(90… in calculate_bandwidth()
881 if (data->fbc_en[i] == 1) { in calculate_bandwidth()
909 if (data->fbc_en[i] == 1) { in calculate_bandwidth()
2820 data->fbc_en[num_displays + 4] = false; in populate_initial_data()
2877 data->fbc_en[num_displays * 2 + j] = false; in populate_initial_data()
2919 data->fbc_en[num_displays + 4] = false; in populate_initial_data()
A Dcalcs_logger.h383 DC_LOG_BANDWIDTH_CALCS(" [bool] fbc_en[%d]:%d\n", i, data->fbc_en[i]); in print_bw_calcs_data()

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