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Searched refs:fclk (Results 1 – 25 of 54) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/
A Ddml2_mcg_dcn4.c54 if (soc_bb->clk_table.fclk.num_clk_values == 2) { in build_min_clk_table_fine_grained()
59 min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[0]; in build_min_clk_table_fine_grained()
76 …am_bw_table.entries[i].min_fclk_khz, soc_bb->clk_table.fclk.clk_values_khz, soc_bb->clk_table.fclk… in build_min_clk_table_fine_grained()
108 min_table->dram_bw_table.entries[i].min_fclk_khz > min_table->max_clocks_khz.fclk) { in build_min_clk_table_fine_grained()
140 min_table->dram_bw_table.entries[i].min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[i]; in build_min_clk_table_coarse_grained()
155 if (soc_bb->clk_table.dcfclk.num_clk_values < 2 || soc_bb->clk_table.fclk.num_clk_values < 2) in build_min_clock_table()
165 if (soc_bb->clk_table.fclk.num_clk_values == 2) { in build_min_clock_table()
169 if (soc_bb->clk_table.fclk.num_clk_values == soc_bb->clk_table.dcfclk.num_clk_values && in build_min_clock_table()
170 soc_bb->clk_table.fclk.num_clk_values == soc_bb->clk_table.uclk.num_clk_values) in build_min_clock_table()
190 …min_table->max_clocks_khz.fclk = soc_bb->clk_table.fclk.clk_values_khz[soc_bb->clk_table.fclk.num_… in build_min_clock_table()
/drivers/usb/host/
A Dehci-sh.c13 struct clk *iclk, *fclk; member
114 priv->fclk = devm_clk_get(&pdev->dev, "usb_fck"); in ehci_hcd_sh_probe()
115 if (IS_ERR(priv->fclk)) in ehci_hcd_sh_probe()
116 priv->fclk = NULL; in ehci_hcd_sh_probe()
122 ret = clk_enable(priv->fclk); in ehci_hcd_sh_probe()
144 clk_disable(priv->fclk); in ehci_hcd_sh_probe()
162 clk_disable(priv->fclk); in ehci_hcd_sh_remove()
A Dohci-at91.c54 struct clk *fclk; member
78 clk_set_rate(ohci_at91->fclk, 48000000); in at91_start_clock()
81 clk_prepare_enable(ohci_at91->fclk); in at91_start_clock()
90 clk_disable_unprepare(ohci_at91->fclk); in at91_stop_clock()
215 ohci_at91->fclk = devm_clk_get(dev, "uhpck"); in usb_hcd_at91_probe()
216 if (IS_ERR(ohci_at91->fclk)) { in usb_hcd_at91_probe()
218 retval = PTR_ERR(ohci_at91->fclk); in usb_hcd_at91_probe()
/drivers/media/dvb-frontends/
A Ds5h1420.c39 u32 fclk; member
368 tmp = state->fclk / tmp; in s5h1420_read_status()
475 do_div(val, (state->fclk / 1000)); in s5h1420_setsymbolrate()
530 val = (((-val) * (state->fclk/1000000)) / (1<<24)); in s5h1420_getfreqoffset()
668 state->fclk = 80000000; in s5h1420_set_frontend()
670 state->fclk = 59000000; in s5h1420_set_frontend()
672 state->fclk = 86000000; in s5h1420_set_frontend()
674 state->fclk = 88000000; in s5h1420_set_frontend()
676 state->fclk = 44000000; in s5h1420_set_frontend()
678 …dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1)… in s5h1420_set_frontend()
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A Dcx24110.c231 u32 tmp, fclk, BDRI; in cx24110_set_symbolrate() local
251 fclk=90999000UL/2; in cx24110_set_symbolrate()
255 fclk=60666000UL; in cx24110_set_symbolrate()
259 fclk=80888000UL; in cx24110_set_symbolrate()
263 fclk=90999000UL; in cx24110_set_symbolrate()
265 dprintk("cx24110 debug: fclk %d Hz\n",fclk); in cx24110_set_symbolrate()
275 BDRI=fclk>>2; in cx24110_set_symbolrate()
288 dprintk("fclk = %d\n", fclk); in cx24110_set_symbolrate()
A Dmb86a20s.h22 u32 fclk; member
A Dmb86a20s.c1745 u32 fclk; in mb86a20s_initfe() local
1780 fclk = state->config->fclk; in mb86a20s_initfe()
1781 if (!fclk) in mb86a20s_initfe()
1782 fclk = 32571428; in mb86a20s_initfe()
1792 do_div(pll, 63 * fclk); in mb86a20s_initfe()
1807 __func__, fclk, state->if_freq, (long long)pll); in mb86a20s_initfe()
/drivers/clk/nuvoton/
A Dclk-ma35d1-pll.c146 unsigned long tmp, fout, fclk, diff; in ma35d1_pll_find_closest() local
153 fclk = div_u64(parent_rate * n, m); in ma35d1_pll_find_closest()
156 fclk = div_u64(fclk, 100); in ma35d1_pll_find_closest()
158 if (fclk < PLL_FCLK_MIN_FREQ || in ma35d1_pll_find_closest()
159 fclk > PLL_FCLK_MAX_FREQ) in ma35d1_pll_find_closest()
162 fout = div_u64(fclk, p); in ma35d1_pll_find_closest()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
A Ddml2_dpmm_dcn4.c24 double *fclk, in get_minimum_clocks_for_latency() argument
35 *fclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_fclk_khz; in get_minimum_clocks_for_latency()
329 display_cfg->min_clocks.dcn4x.active.fclk_khz <= state_table->fclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
332 display_cfg->min_clocks.dcn4x.active.fclk_khz = state_table->fclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
343 display_cfg->min_clocks.dcn4x.idle.fclk_khz <= state_table->fclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
346 display_cfg->min_clocks.dcn4x.idle.fclk_khz = state_table->fclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
375 if (state_table->fclk.num_clk_values == 2) { in map_min_clocks_to_dpm()
379 if (state_table->fclk.num_clk_values == state_table->dcfclk.num_clk_values && in map_min_clocks_to_dpm()
380 state_table->fclk.num_clk_values == state_table->uclk.num_clk_values) { in map_min_clocks_to_dpm()
585 ….dcn4x.active.fclk_khz = in_out->soc_bb->clk_table.fclk.clk_values_khz[in_out->soc_bb->clk_table.f… in clamp_fclk_to_max()
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/drivers/clocksource/
A Dtimer-ti-dm.c122 struct clk *fclk; member
417 if (unlikely(!timer) || IS_ERR(timer->fclk)) in omap_dm_timer_set_source()
456 ret = clk_set_parent(timer->fclk, parent); in omap_dm_timer_set_source()
728 if (timer && !IS_ERR(timer->fclk)) in omap_dm_timer_get_fclk()
729 return timer->fclk; in omap_dm_timer_get_fclk()
1139 timer->fclk = devm_clk_get(dev, "fck"); in omap_dm_timer_probe()
1140 if (IS_ERR(timer->fclk)) in omap_dm_timer_probe()
1141 return PTR_ERR(timer->fclk); in omap_dm_timer_probe()
1144 ret = devm_clk_notifier_register(dev, timer->fclk, in omap_dm_timer_probe()
1149 timer->fclk_rate = clk_get_rate(timer->fclk); in omap_dm_timer_probe()
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/drivers/gpu/drm/hisilicon/hibmc/dp/
A Ddp_hw.c53 u32 fclk; /* flink_clock */ in hibmc_dp_set_sst() local
55 fclk = dp->link.cap.link_rate * HIBMC_DP_LINK_RATE_CAL; in hibmc_dp_set_sst()
61 htotal_size = htotal_int * fclk / (HIBMC_DP_SYMBOL_PER_FCLK * (mode->clock / 1000)); in hibmc_dp_set_sst()
64 hblank_size = hblank_int * fclk * 9947 / in hibmc_dp_set_sst()
69 drm_dbg_dp(dp->dev, "flink_clock %u pixel_clock %d", fclk, mode->clock / 1000); in hibmc_dp_set_sst()
/drivers/pwm/
A Dpwm-omap-dmtimer.c154 struct clk *fclk; in pwm_omap_dmtimer_config() local
163 fclk = omap->pdata->get_fclk(omap->dm_timer); in pwm_omap_dmtimer_config()
164 if (!fclk) { in pwm_omap_dmtimer_config()
169 clk_rate = clk_get_rate(fclk); in pwm_omap_dmtimer_config()
/drivers/i2c/busses/
A Di2c-omap.c357 struct clk *fclk; in omap_i2c_init() local
376 fclk = clk_get(omap->dev, "fck"); in omap_i2c_init()
377 if (IS_ERR(fclk)) { in omap_i2c_init()
378 error = PTR_ERR(fclk); in omap_i2c_init()
384 fclk_rate = clk_get_rate(fclk); in omap_i2c_init()
385 clk_put(fclk); in omap_i2c_init()
415 fclk = clk_get(omap->dev, "fck"); in omap_i2c_init()
416 if (IS_ERR(fclk)) { in omap_i2c_init()
417 error = PTR_ERR(fclk); in omap_i2c_init()
422 fclk_rate = clk_get_rate(fclk) / 1000; in omap_i2c_init()
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/drivers/iio/adc/
A Dad7124.c255 unsigned int fclk, odr_sel_bits; in ad7124_set_channel_odr() local
257 fclk = clk_get_rate(st->mclk); in ad7124_set_channel_odr()
265 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32); in ad7124_set_channel_odr()
275 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32); in ad7124_set_channel_odr()
1114 unsigned int fclk, power_mode; in ad7124_setup() local
1117 fclk = clk_get_rate(st->mclk); in ad7124_setup()
1118 if (!fclk) in ad7124_setup()
1124 fclk); in ad7124_setup()
1125 if (fclk != ad7124_master_clk_freq_hz[power_mode]) { in ad7124_setup()
1126 ret = clk_set_rate(st->mclk, fclk); in ad7124_setup()
A Dad7192.c209 u32 fclk; member
517 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_clock_setup()
529 st->fclk = clk_get_rate(st->mclk); in ad7192_clock_setup()
530 if (!ad7192_valid_external_frequency(st->fclk)) in ad7192_clock_setup()
543 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_clock_setup()
559 st->fclk = clk_get_rate(st->mclk); in ad7192_clock_setup()
560 if (!ad7192_valid_external_frequency(st->fclk)) in ad7192_clock_setup()
763 return DIV_ROUND_CLOSEST(st->fclk, in ad7192_compute_f_adc()
771 return DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_f_adc()
985 div = st->fclk / (val * ad7192_get_f_order(st) * 1024); in __ad7192_write_raw()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c575 if (clock_table->DfPstateTable[i].fclk != 0) { in vg_clk_mgr_helper_populate_bw_params()
590 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
595 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
632 { .fclk = 400, .memclk = 400, .voltage = 2800 },
633 { .fclk = 400, .memclk = 400, .voltage = 2800 },
634 { .fclk = 400, .memclk = 400, .voltage = 2800 },
635 { .fclk = 400, .memclk = 400, .voltage = 2800 }
/drivers/net/hamradio/
A Dbaycom_epp.c167 unsigned int fclk; member
306 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps, in eppconfig()
307 (bc->cfg.fclk + 8 * bc->cfg.bps) / (16 * bc->cfg.bps), in eppconfig()
984 bc->cfg.fclk = simple_strtoul(cp+5, NULL, 0); in baycom_setmode()
985 if (bc->cfg.fclk < 1000000) in baycom_setmode()
986 bc->cfg.fclk = 1000000; in baycom_setmode()
987 if (bc->cfg.fclk > 25000000) in baycom_setmode()
988 bc->cfg.fclk = 25000000; in baycom_setmode()
1083 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps, in baycom_siocdevprivate()
1206 bc->cfg.fclk = 19666600; in baycom_epp_dev_setup()
/drivers/mmc/host/
A Domap.c131 struct clk * fclk; member
194 clk_enable(host->fclk); in mmc_omap_fclk_enable()
196 clk_disable(host->fclk); in mmc_omap_fclk_enable()
1431 host->fclk = clk_get(&pdev->dev, "fck"); in mmc_omap_probe()
1432 if (IS_ERR(host->fclk)) { in mmc_omap_probe()
1433 ret = PTR_ERR(host->fclk); in mmc_omap_probe()
1437 ret = clk_prepare(host->fclk); in mmc_omap_probe()
1511 clk_unprepare(host->fclk); in mmc_omap_probe()
1513 clk_put(host->fclk); in mmc_omap_probe()
1535 clk_unprepare(host->fclk); in mmc_omap_remove()
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A Domap_hsmmc.c175 struct clk *fclk; member
525 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); in calc_divisor()
572 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) in omap_hsmmc_set_clock()
1432 host->clk_rate = clk_get_rate(host->fclk); in omap_hsmmc_request()
1838 host->fclk = devm_clk_get(&pdev->dev, "fck"); in omap_hsmmc_probe()
1839 if (IS_ERR(host->fclk)) { in omap_hsmmc_probe()
1840 ret = PTR_ERR(host->fclk); in omap_hsmmc_probe()
1841 host->fclk = NULL; in omap_hsmmc_probe()
/drivers/clk/zynq/
A Dclkc.c103 static void __init zynq_clk_register_fclk(enum zynq_clk fclk, in zynq_clk_register_fclk() argument
147 clks[fclk] = clk_register_gate(NULL, clk_name, in zynq_clk_register_fclk()
152 if (clk_prepare_enable(clks[fclk])) in zynq_clk_register_fclk()
154 fclk - fclk0); in zynq_clk_register_fclk()
171 clks[fclk] = ERR_PTR(-ENOMEM); in zynq_clk_register_fclk()
/drivers/spi/
A Dspi-ti-qspi.c49 struct clk *fclk; member
176 clk_rate = clk_get_rate(qspi->fclk); in ti_qspi_setup_clk()
840 qspi->fclk = devm_clk_get(&pdev->dev, "fck"); in ti_qspi_probe()
841 if (IS_ERR(qspi->fclk)) { in ti_qspi_probe()
842 ret = PTR_ERR(qspi->fclk); in ti_qspi_probe()
/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Drenoir_ppt.c914 uint32_t sclk = 0, socclk = 0, fclk = 0; in renior_set_dpm_profile_freq() local
932 fclk = RENOIR_UMD_PSTATE_FCLK; in renior_set_dpm_profile_freq()
934 renoir_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk); in renior_set_dpm_profile_freq()
936 renoir_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk, NULL); in renior_set_dpm_profile_freq()
949 if (fclk) in renior_set_dpm_profile_freq()
950 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_FCLK, fclk, fclk, false); in renior_set_dpm_profile_freq()
/drivers/clk/samsung/
A Dclk-exynos4.c1042 struct samsung_fixed_rate_clock fclk; in exynos4_clk_register_finpll() local
1059 fclk.id = CLK_FIN_PLL; in exynos4_clk_register_finpll()
1060 fclk.name = "fin_pll"; in exynos4_clk_register_finpll()
1061 fclk.parent_name = NULL; in exynos4_clk_register_finpll()
1062 fclk.flags = 0; in exynos4_clk_register_finpll()
1063 fclk.fixed_rate = finpll_f; in exynos4_clk_register_finpll()
1064 samsung_clk_register_fixed_rate(ctx, &fclk, 1); in exynos4_clk_register_finpll()
/drivers/usb/gadget/udc/
A Dat91_udc.c906 clk_enable(udc->fclk); in clk_on()
915 clk_disable(udc->fclk); in clk_off()
1849 udc->fclk = devm_clk_get(dev, "hclk"); in at91udc_probe()
1850 if (IS_ERR(udc->fclk)) in at91udc_probe()
1851 return PTR_ERR(udc->fclk); in at91udc_probe()
1854 clk_set_rate(udc->fclk, 48000000); in at91udc_probe()
1855 retval = clk_prepare(udc->fclk); in at91udc_probe()
1921 clk_unprepare(udc->fclk); in at91udc_probe()
1948 clk_unprepare(udc->fclk); in at91udc_remove()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c124 dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels; in override_dml_init_with_values_from_smu()
126 if (i < dml_clk_table->fclk.num_clk_values) { in override_dml_init_with_values_from_smu()
130 dml_clk_table->fclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.fclk_mhz * 1000; in override_dml_init_with_values_from_smu()
131 dml_clk_table->fclk.num_clk_values = i + 1; in override_dml_init_with_values_from_smu()
133 dml_clk_table->fclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()
134 dml_clk_table->fclk.num_clk_values = i; in override_dml_init_with_values_from_smu()
137 dml_clk_table->fclk.clk_values_khz[i] = dc_clk_table->entries[i].fclk_mhz * 1000; in override_dml_init_with_values_from_smu()
140 dml_clk_table->fclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()

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