fclk_p_state_change_support (reference) in projects: drivers - OpenGrok search results

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Searched refs:fclk_p_state_change_support (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A D	dcn32_clk_mgr.c	546 if (!new_clocks->fclk_p_state_change_support) { in dcn32_auto_dpm_test_log() 637 bool fclk_p_state_change_support; in dcn32_update_clocks() local 661 …k_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support; in dcn32_update_clocks() 663 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support; in dcn32_update_clocks() 665 …d_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_stat… in dcn32_update_clocks() 667 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support; in dcn32_update_clocks() 670 …mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support) { in dcn32_update_clocks() 735 …if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_pr… in dcn32_update_clocks() 739 …e->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support && upda… in dcn32_update_clocks() 1087 else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support) in dcn32_are_clock_states_equal()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A D	dcn401_clk_mgr.c	448 if (!new_clocks->fclk_p_state_change_support) in dcn401_auto_dpm_test_log() 798 bool fclk_p_state_change_support, uclk_p_state_change_support; in dcn401_build_update_bandwidth_clocks_sequence() local 815 …k_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support; in dcn401_build_update_bandwidth_clocks_sequence() 816 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support \|\| (total_plane_count == 0); in dcn401_build_update_bandwidth_clocks_sequence() 817 …if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fc… in dcn401_build_update_bandwidth_clocks_sequence() 818 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support; in dcn401_build_update_bandwidth_clocks_sequence() 833 …if (!clk_mgr_base->clks.fclk_p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_interna… in dcn401_build_update_bandwidth_clocks_sequence() 960 if (clk_mgr_base->clks.fclk_p_state_change_support) { in dcn401_build_update_bandwidth_clocks_sequence() 969 if (clk_mgr_base->clks.fclk_p_state_change_support) { in dcn401_build_update_bandwidth_clocks_sequence() 1447 else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support) in dcn401_are_clock_states_equal()
/drivers/gpu/drm/amd/display/dc/dml2/
A D	dml2_utils.c	`289 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false; in dml2_calculate_rq_and_dlg_params() 291 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; in dml2_calculate_rq_and_dlg_params()`
/drivers/gpu/drm/amd/display/dc/
A D	dc.h	`665 bool fclk_p_state_change_support; member`
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A D	dcn32_fpu.c	`1678 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false; in dcn32_calculate_dlg_params() 1680 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; in dcn32_calculate_dlg_params() 1775 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; in dcn32_calculate_dlg_params()`
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A D	dml21_translation_helper.c	`1161 …context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = in_ctx->v21.mode_programming.programming-… in dml21_copy_clocks_to_dc_state()`
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A D	dcn32_hwseq.c	`757 clocks->fclk_p_state_change_support = true; in dcn32_initialize_min_clocks()`
/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A D	dcn401_hwseq.c	`74 clocks->fclk_p_state_change_support = true; in dcn401_initialize_min_clocks()`

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