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Searched refs:fclk_pstate (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/
A Ddcn401_hubbub.c353 > hubbub2->watermarks.dcn4x.a.fclk_pstate) { in hubbub401_program_pstate_watermarks()
354 hubbub2->watermarks.dcn4x.a.fclk_pstate = in hubbub401_program_pstate_watermarks()
355 watermarks->dcn4x.a.fclk_pstate; in hubbub401_program_pstate_watermarks()
360 watermarks->dcn4x.a.fclk_pstate, watermarks->dcn4x.a.fclk_pstate); in hubbub401_program_pstate_watermarks()
361 } else if (watermarks->dcn4x.a.fclk_pstate in hubbub401_program_pstate_watermarks()
362 < hubbub2->watermarks.dcn4x.a.fclk_pstate) in hubbub401_program_pstate_watermarks()
368 hubbub2->watermarks.dcn4x.b.fclk_pstate = in hubbub401_program_pstate_watermarks()
369 watermarks->dcn4x.b.fclk_pstate; in hubbub401_program_pstate_watermarks()
374 watermarks->dcn4x.b.fclk_pstate, watermarks->dcn4x.b.fclk_pstate); in hubbub401_program_pstate_watermarks()
375 } else if (watermarks->dcn4x.b.fclk_pstate in hubbub401_program_pstate_watermarks()
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/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_dchub_registers.h163 uint32_t fclk_pstate; member
A Ddml_top_display_cfg_types.h421 enum dml2_twait_budgeting_setting fclk_pstate; member
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/
A Ddml2_pmo_dcn3.c557 …stream_descriptor->overrides.hw.twait_budgeting.fclk_pstate == dml2_twait_budgeting_setting_if_nee… in pmo_dcn3_init_for_pstate_support()
560 …if (stream_descriptor->overrides.hw.twait_budgeting.fclk_pstate == dml2_twait_budgeting_setting_tr… in pmo_dcn3_init_for_pstate_support()
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0.c1312 fclk_min = fclk_max = pstate_table->fclk_pstate.standard; in smu_v14_0_set_performance_level()
1326 fclk_min = fclk_max = pstate_table->fclk_pstate.peak; in smu_v14_0_set_performance_level()
1416 pstate_table->fclk_pstate.curr.min = fclk_min; in smu_v14_0_set_performance_level()
1417 pstate_table->fclk_pstate.curr.max = fclk_max; in smu_v14_0_set_performance_level()
A Dsmu_v14_0_2_ppt.c1623 pstate_table->fclk_pstate.min = fclk_table->min; in smu_v14_0_2_populate_umd_state_clk()
1624 pstate_table->fclk_pstate.peak = fclk_table->max; in smu_v14_0_2_populate_umd_state_clk()
1635 pstate_table->fclk_pstate.standard = fclk_table->min; in smu_v14_0_2_populate_umd_state_clk()
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0.c1649 fclk_min = fclk_max = pstate_table->fclk_pstate.standard; in smu_v13_0_set_performance_level()
1663 fclk_min = fclk_max = pstate_table->fclk_pstate.peak; in smu_v13_0_set_performance_level()
1766 pstate_table->fclk_pstate.curr.min = fclk_min; in smu_v13_0_set_performance_level()
1767 pstate_table->fclk_pstate.curr.max = fclk_max; in smu_v13_0_set_performance_level()
A Dsmu_v13_0_7_ppt.c2329 pstate_table->fclk_pstate.min = fclk_table->min; in smu_v13_0_7_populate_umd_state_clk()
2330 pstate_table->fclk_pstate.peak = fclk_table->max; in smu_v13_0_7_populate_umd_state_clk()
2341 pstate_table->fclk_pstate.standard = fclk_table->min; in smu_v13_0_7_populate_umd_state_clk()
A Dsmu_v13_0_0_ppt.c2343 pstate_table->fclk_pstate.min = fclk_table->min; in smu_v13_0_0_populate_umd_state_clk()
2344 pstate_table->fclk_pstate.peak = fclk_table->max; in smu_v13_0_0_populate_umd_state_clk()
2355 pstate_table->fclk_pstate.standard = fclk_table->min; in smu_v13_0_0_populate_umd_state_clk()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
A Ddml2_dpmm_dcn4.c751 …dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].fclk_pstate = (int unsigned)(mode_lib->mp.Water… in dpmm_dcn4_map_watermarks()
767 …dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_B].fclk_pstate = (int unsigned)(mode_lib->mp.Water… in dpmm_dcn4_map_watermarks()
/drivers/gpu/drm/amd/pm/swsmu/inc/
A Damdgpu_smu.h481 struct pstates_clk_freq fclk_pstate; member
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c1105 …eam_descriptors[disp_cfg_stream_location].overrides.hw.twait_budgeting.fclk_pstate = dml2_twait_bu… in dml21_map_dc_state_into_dml_display_cfg()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_dcn4_calcs.c12158 …wm_regs->fclk_pstate = (int unsigned)(mode_lib->mp.Watermark.FCLKChangeWatermark * refclk_freq_in_… in rq_dlg_get_wm_regs()

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