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/drivers/scsi/aic7xxx/
A Dqueue.h146 #define SLIST_NEXT(elm, field) ((elm)->field.sle_next) argument
157 SLIST_NEXT(SLIST_NEXT(curelm, field), field); \
282 LIST_NEXT((listelm), field)->field.le_prev = \
289 (elm)->field.le_prev = (listelm)->field.le_prev; \
302 #define LIST_NEXT(elm, field) ((elm)->field.le_next) argument
306 LIST_NEXT((elm), field)->field.le_prev = \
308 *(elm)->field.le_prev = LIST_NEXT((elm), field); \
353 TAILQ_NEXT((elm), field)->field.tqe_prev = \
395 TAILQ_NEXT((elm), field)->field.tqe_prev = \
492 CIRCLEQ_PREV(CIRCLEQ_NEXT((elm), field), field) = \
[all …]
A Daic79xx.reg134 field {
665 field RDY 0x01
1143 field DPE 0x80
1144 field SSE 0x40
1145 field RMA 0x20
1146 field RTA 0x10
1150 field DPR 0x01
1161 field DPE 0x80
1162 field SSE 0x40
1163 field RMA 0x20
[all …]
A Daic7xxx.reg88 field DFON 0x80
121 field CDI 0x80
122 field IOI 0x40
123 field MSGI 0x20
124 field ATNI 0x10
125 field SELI 0x08
126 field BSYI 0x04
127 field REQI 0x02
128 field ACKI 0x01
152 field CDO 0x80
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/
A Ddml2_debug.h14 #define _BOOL_FORMAT(field) "%s", field ? "true" : "false" argument
15 #define _UINT_FORMAT(field) "%u", field argument
16 #define _INT_FORMAT(field) "%d", field argument
17 #define _DOUBLE_FORMAT(field) "%lf", field argument
28 DML_LOG_INTERNAL(#field" = "format(field)); \
143 #define DML_LOG_DEBUG_BOOL(field) _LOG_SCALAR(field, _BOOL_FORMAT) argument
144 #define DML_LOG_DEBUG_UINT(field) _LOG_SCALAR(field, _UINT_FORMAT) argument
145 #define DML_LOG_DEBUG_INT(field) _LOG_SCALAR(field, _INT_FORMAT) argument
146 #define DML_LOG_DEBUG_DOUBLE(field) _LOG_SCALAR(field, _DOUBLE_FORMAT) argument
147 #define DML_LOG_DEBUG_ARRAY_BOOL(field, size) _LOG_ARRAY(field, size, _BOOL_FORMAT) argument
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/drivers/infiniband/hw/mlx5/
A Dcong.c184 MLX5_SET(cong_control_r_roce_ecn_rp, field, in mlx5_ib_set_cc_param_mask_val()
189 MLX5_SET(cong_control_r_roce_ecn_rp, field, in mlx5_ib_set_cc_param_mask_val()
194 MLX5_SET(cong_control_r_roce_ecn_rp, field, in mlx5_ib_set_cc_param_mask_val()
199 MLX5_SET(cong_control_r_roce_ecn_rp, field, in mlx5_ib_set_cc_param_mask_val()
204 MLX5_SET(cong_control_r_roce_ecn_rp, field, in mlx5_ib_set_cc_param_mask_val()
209 MLX5_SET(cong_control_r_roce_ecn_rp, field, in mlx5_ib_set_cc_param_mask_val()
214 MLX5_SET(cong_control_r_roce_ecn_rp, field, in mlx5_ib_set_cc_param_mask_val()
219 MLX5_SET(cong_control_r_roce_ecn_rp, field, in mlx5_ib_set_cc_param_mask_val()
224 MLX5_SET(cong_control_r_roce_ecn_rp, field, in mlx5_ib_set_cc_param_mask_val()
297 void *field; in mlx5_ib_get_cc_params() local
[all …]
/drivers/xen/xen-pciback/
A Dconf_space.c47 const struct config_field *field = entry->field; in DEFINE_PCI_CONFIG() local
53 if (field->u.b.read) in DEFINE_PCI_CONFIG()
58 if (field->u.w.read) in DEFINE_PCI_CONFIG()
75 const struct config_field *field = entry->field; in conf_space_write() local
180 field = cfg_entry->field; in xen_pcibk_config_read()
220 field = cfg_entry->field; in xen_pcibk_config_write()
341 field = cfg_entry->field; in xen_pcibk_config_free_dyn_fields()
344 field->clean((struct config_field *)field); in xen_pcibk_config_free_dyn_fields()
366 field = cfg_entry->field; in xen_pcibk_config_reset_dev()
386 field = cfg_entry->field; in xen_pcibk_config_free_dev()
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/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu_helper.h137 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT argument
138 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK argument
142 (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
156 reg, field)
160 reg, field)
169 reg, field, fieldval))
174 reg, field, fieldval))
185 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
211 PHM_FIELD_MASK(reg, field))
225 PHM_FIELD_MASK(reg, field))
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/drivers/net/ethernet/mellanox/mlx4/
A Dfw.c209 u8 field; in mlx4_QUERY_FUNC() local
443 field = 0; in mlx4_QUERY_FUNC_CAP_wrapper()
464 field = min( in mlx4_QUERY_FUNC_CAP_wrapper()
729 u8 field; in mlx4_QUERY_DEV_CAP() local
879 if (!field) in mlx4_QUERY_DEV_CAP()
890 if (field) { in mlx4_QUERY_DEV_CAP()
950 field = 3; in mlx4_QUERY_DEV_CAP()
1190 u8 field; in mlx4_QUERY_PORT() local
1280 u8 field; in mlx4_QUERY_DEV_CAP_wrapper() local
1492 u16 field; in mlx4_get_slave_pkey_gid_tbl_len() local
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/drivers/infiniband/hw/hfi1/
A Dexp_rcv.h18 #define EXP_TID_GET(tid, field) \ argument
19 (((tid) >> EXP_TID_TID##field##_SHIFT) & EXP_TID_TID##field##_MASK)
21 #define EXP_TID_SET(field, value) \ argument
23 EXP_TID_TID##field##_SHIFT)
26 EXP_TID_TID##field##_SHIFT); \
29 EXP_TID_CLEAR(tid, field); \
58 #define KDETH_GET(val, field) \ argument
59 (((le32_to_cpu((val))) >> KDETH_##field##_SHIFT) & KDETH_##field##_MASK)
62 dwval &= ~(KDETH_##field##_MASK << KDETH_##field##_SHIFT); \
64 KDETH_##field##_SHIFT); \
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/drivers/hid/
A Dhid-input.c825 if (field->dpad) { in hidinput_configure_usage()
1526 if (!field->hidinput) in hidinput_hid_event()
1553 field->logical_minimum < field->logical_maximum) { in hidinput_hid_event()
1745 *field = report->field[i]; in hidinput_find_field()
1747 if ((*field)->usage[j].type == type && (*field)->usage[j].code == code) in hidinput_find_field()
1764 field = report->field[i]; in hidinput_get_led_field()
1767 return field; in hidinput_get_led_field()
1785 field = report->field[i]; in hidinput_count_leds()
1788 field->value[j]) in hidinput_count_leds()
1807 if (!field) in hidinput_led_worker()
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A Dhid-core.c137 report->field[field->index] = field; in hid_register_field()
138 field->usage = (struct hid_usage *)(field + 1); in hid_register_field()
139 field->value = (s32 *)(field->usage + usages); in hid_register_field()
1182 field = rep->field[i]; in hid_apply_multiplier()
1701 field = entry->field; in hid_process_report()
1715 field = report->field[a]; in hid_process_report()
1718 memcpy(field->value, field->new_value, in hid_process_report()
1724 field = report->field[a]; in hid_process_report()
1749 entry->field = field; in __hid_insert_field_entry()
1781 field = report->field[a]; in hid_report_process_ordering()
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A Dhid-dr.c53 drff->report->field[0]->value[0] = 0x51; in drff_play()
54 drff->report->field[0]->value[1] = 0x00; in drff_play()
55 drff->report->field[0]->value[2] = weak; in drff_play()
59 drff->report->field[0]->value[0] = 0xfa; in drff_play()
60 drff->report->field[0]->value[1] = 0xfe; in drff_play()
62 drff->report->field[0]->value[0] = 0xf3; in drff_play()
63 drff->report->field[0]->value[1] = 0x00; in drff_play()
66 drff->report->field[0]->value[2] = 0x00; in drff_play()
67 drff->report->field[0]->value[4] = 0x00; in drff_play()
120 drff->report->field[0]->value[0] = 0xf3; in drff_init()
[all …]
A Dhid-gaff.c44 gaff->report->field[0]->value[0] = 0x51; in hid_gaff_play()
45 gaff->report->field[0]->value[1] = 0x0; in hid_gaff_play()
46 gaff->report->field[0]->value[2] = right; in hid_gaff_play()
47 gaff->report->field[0]->value[3] = 0; in hid_gaff_play()
48 gaff->report->field[0]->value[4] = left; in hid_gaff_play()
49 gaff->report->field[0]->value[5] = 0; in hid_gaff_play()
53 gaff->report->field[0]->value[0] = 0xfa; in hid_gaff_play()
54 gaff->report->field[0]->value[1] = 0xfe; in hid_gaff_play()
55 gaff->report->field[0]->value[2] = 0x0; in hid_gaff_play()
56 gaff->report->field[0]->value[4] = 0x0; in hid_gaff_play()
[all …]
A Dhid-lg3ff.c56 memset(report->field[0]->value, 0, in hid_lg3ff_play()
69 report->field[0]->value[0] = 0x51; in hid_lg3ff_play()
94 report->field[0]->value[0] = 0x51; in hid_lg3ff_set_autocenter()
95 report->field[0]->value[1] = 0x00; in hid_lg3ff_set_autocenter()
96 report->field[0]->value[2] = 0x00; in hid_lg3ff_set_autocenter()
97 report->field[0]->value[3] = 0x7F; in hid_lg3ff_set_autocenter()
98 report->field[0]->value[4] = 0x7F; in hid_lg3ff_set_autocenter()
99 report->field[0]->value[31] = 0x00; in hid_lg3ff_set_autocenter()
100 report->field[0]->value[32] = 0x00; in hid_lg3ff_set_autocenter()
101 report->field[0]->value[33] = 0x7F; in hid_lg3ff_set_autocenter()
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A Dhid-lg2ff.c36 lg2ff->report->field[0]->value[0] = 0x51; in play_effect()
37 lg2ff->report->field[0]->value[2] = weak; in play_effect()
40 lg2ff->report->field[0]->value[0] = 0xf3; in play_effect()
41 lg2ff->report->field[0]->value[2] = 0x00; in play_effect()
82 report->field[0]->value[0] = 0xf3; in lg2ff_init()
83 report->field[0]->value[1] = 0x00; in lg2ff_init()
84 report->field[0]->value[2] = 0x00; in lg2ff_init()
85 report->field[0]->value[3] = 0x00; in lg2ff_init()
86 report->field[0]->value[4] = 0x00; in lg2ff_init()
87 report->field[0]->value[5] = 0x00; in lg2ff_init()
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A Dhid-sensor-hub.c90 info->units = field->unit; in sensor_hub_fill_attr_info()
92 info->size = (field->report_size * field->report_count)/8; in sensor_hub_fill_attr_info()
356 struct hid_field *field; in hid_sensor_get_usage_index() local
363 field = report->field[field_index]; in hid_sensor_get_usage_index()
383 struct hid_field *field; in sensor_hub_input_get_attribute_info() local
398 field = report->field[i]; in sensor_hub_input_get_attribute_info()
399 if (field->maxusage) { in sensor_hub_input_get_attribute_info()
403 field->usage[0].hid == in sensor_hub_input_get_attribute_info()
412 field); in sensor_hub_input_get_attribute_info()
499 report->field[i]->usage->hid, in sensor_hub_raw_event()
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A Dhid-multitouch.c638 struct hid_field *field; in mt_allocate_report_data() local
654 field = report->field[r]; in mt_allocate_report_data()
1199 struct hid_field *field, in mt_process_mt_event() argument
1242 struct hid_field *field; in mt_touch_report() local
1292 field = report->field[r]; in mt_touch_report()
1293 count = field->report_count; in mt_touch_report()
1300 &field->usage[n], field->value[n], in mt_touch_report()
1527 struct hid_field *field = report->field[0]; in mt_report() local
1537 if (field && field->hidinput && field->hidinput->input) in mt_report()
1589 field->value[index] = max; in mt_need_to_apply_feature()
[all …]
/drivers/clk/st/
A Dclkgen.h22 struct clkgen_field *field) in clkgen_read() argument
24 return (readl(base + field->offset) >> field->shift) & field->mask; in clkgen_read()
28 static inline void clkgen_write(void __iomem *base, struct clkgen_field *field, in clkgen_write() argument
31 writel((readl(base + field->offset) & in clkgen_write()
32 ~(field->mask << field->shift)) | (val << field->shift), in clkgen_write()
33 base + field->offset); in clkgen_write()
44 #define CLKGEN_READ(pll, field) clkgen_read(pll->regs_base, \ argument
45 &pll->data->field)
47 #define CLKGEN_WRITE(pll, field, val) clkgen_write(pll->regs_base, \ argument
48 &pll->data->field, val)
/drivers/md/
A Ddm-init.c117 char *field[4]; in dm_parse_table_entry() local
120 field[0] = str; in dm_parse_table_entry()
123 field[i + 1] = str_field_delimit(&field[i], ' '); in dm_parse_table_entry()
124 if (!field[i + 1]) in dm_parse_table_entry()
195 char *field[5]; in dm_parse_device_entry() local
199 field[0] = str; in dm_parse_device_entry()
202 field[i+1] = str_field_delimit(&field[i], ','); in dm_parse_device_entry()
203 if (!field[i+1]) in dm_parse_device_entry()
214 if (strlen(field[2])) { in dm_parse_device_entry()
222 if (!strcmp(field[3], "ro")) in dm_parse_device_entry()
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/drivers/acpi/acpica/
A Dexfield.c137 (obj_desc->field.region_obj->region.space_id == in acpi_ex_read_data_from_field()
194 (obj_desc->field.region_obj->region.space_id == in acpi_ex_read_data_from_field()
202 (obj_desc->field.region_obj->region.space_id == in acpi_ex_read_data_from_field()
210 obj_desc->field.bit_length)); in acpi_ex_read_data_from_field()
213 obj_desc->field.region_obj->field.internal_pcc_buffer + in acpi_ex_read_data_from_field()
214 obj_desc->field.base_byte_offset, in acpi_ex_read_data_from_field()
295 (obj_desc->field.region_obj->region.space_id == in acpi_ex_write_data_to_field()
333 memcpy(obj_desc->field.region_obj->field.internal_pcc_buffer + in acpi_ex_write_data_to_field()
334 obj_desc->field.base_byte_offset, in acpi_ex_write_data_to_field()
346 (u64 *)obj_desc->field. in acpi_ex_write_data_to_field()
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/drivers/cdx/controller/
A Dbitfield.h18 #define CDX_VAL(field, attribute) field ## _ ## attribute argument
20 #define CDX_LOW_BIT(field) CDX_VAL(field, LBN) argument
22 #define CDX_WIDTH(field) CDX_VAL(field, WIDTH) argument
24 #define CDX_HIGH_BIT(field) (CDX_LOW_BIT(field) + CDX_WIDTH(field) - 1) argument
39 #define CDX_DWORD_FIELD(dword, field) \ argument
40 (FIELD_GET(GENMASK(CDX_HIGH_BIT(field), CDX_LOW_BIT(field)), \
47 #define CDX_INSERT_FIELD(field, value) \ argument
48 (FIELD_PREP(GENMASK(CDX_HIGH_BIT(field), \
49 CDX_LOW_BIT(field)), value))
/drivers/gpu/nova-core/regs/
A Dmacros.rs155 .field(&format_args!("0x{0:x}", &self.0))
178 $($hi:tt:$lo:tt $field:ident as $type:tt
231 @leaf_accessor $name $hi:$lo $field as bool
249 register!(@leaf_accessor $name $hi:$lo $field as $type
263 register!(@leaf_accessor $name $hi:$lo $field as $type
283 const [<$field:upper _SHIFT>]: u32 = Self::[<$field:upper _MASK>].trailing_zeros();
291 pub(crate) fn $field(self) -> $res_type {
293 const MASK: u32 = $name::[<$field:upper _MASK>];
296 let field = ((self.0 & MASK) >> SHIFT);
298 $process(field)
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/drivers/gpu/drm/amd/include/
A Dcgs_common.h120 #define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT argument
121 #define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK argument
123 #define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \ argument
124 (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \
125 (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field))))
127 #define CGS_REG_GET_FIELD(value, reg, field) \ argument
128 (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field))
130 #define CGS_WREG32_FIELD(device, reg, field, val) \ argument
131 …egister(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, fi…
133 #define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \ argument
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/drivers/net/ethernet/sfc/falcon/
A Dbitfield.h45 #define EF4_VAL(field, attribute) field ## _ ## attribute argument
47 #define EF4_LOW_BIT(field) EF4_VAL(field, LBN) argument
49 #define EF4_WIDTH(field) EF4_VAL(field, WIDTH) argument
51 #define EF4_HIGH_BIT(field) (EF4_LOW_BIT(field) + EF4_WIDTH(field) - 1) argument
170 EF4_HIGH_BIT(field))
174 EF4_HIGH_BIT(field))
178 EF4_HIGH_BIT(field))
182 EF4_HIGH_BIT(field))
186 EF4_HIGH_BIT(field))
267 EF4_HIGH_BIT(field), value)
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/drivers/clk/sophgo/
A Dclk-cv18xx-common.c14 struct cv1800_clk_regbit *field) in cv1800_clk_setbit() argument
16 u32 mask = BIT(field->shift); in cv1800_clk_setbit()
22 value = readl(common->base + field->reg); in cv1800_clk_setbit()
23 writel(value | mask, common->base + field->reg); in cv1800_clk_setbit()
31 struct cv1800_clk_regbit *field) in cv1800_clk_clearbit() argument
33 u32 mask = BIT(field->shift); in cv1800_clk_clearbit()
39 value = readl(common->base + field->reg); in cv1800_clk_clearbit()
40 writel(value & ~mask, common->base + field->reg); in cv1800_clk_clearbit()
48 struct cv1800_clk_regbit *field) in cv1800_clk_checkbit() argument
50 return readl(common->base + field->reg) & BIT(field->shift); in cv1800_clk_checkbit()

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