| /drivers/media/tuners/ |
| A D | mt20xx.c | 108 unsigned int fref,lo1,lo1n,lo1a,s,sel,lo1freq, desired_lo1, in mt2032_compute_freq() local
111 fref= 5250 *1000; //5.25MHz in mt2032_compute_freq()
114 lo1=(2*(desired_lo1/1000)+(fref/1000)) / (2*fref/1000); in mt2032_compute_freq()
136 lo1freq=(lo1a+8*lo1n)*fref; in mt2032_compute_freq()
142 lo2=(desired_lo2)/fref; in mt2032_compute_freq()
145 lo2num=((desired_lo2/1000)%(fref/1000))* 3780/(fref/1000); //scale to fit in 32bit arith in mt2032_compute_freq()
146 lo2freq=(lo2a+8*lo2n)*fref + lo2num*(fref/1000)/3780*1000; in mt2032_compute_freq()
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| /drivers/clk/ |
| A D | clk-clps711x.c | 47 u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi, fref = 0; in clps711x_clk_init_dt() local
51 WARN_ON(of_property_read_u32(np, "startup-frequency", &fref)); in clps711x_clk_init_dt()
65 if (((tmp >= 10) && (tmp <= 50)) || !fref) in clps711x_clk_init_dt()
68 f_pll = fref; in clps711x_clk_init_dt()
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| A D | clk-xgene.c | 75 unsigned long fref; in xgene_clk_pll_recalc_rate() local
101 fref = parent_rate / nref; in xgene_clk_pll_recalc_rate()
102 fvco = fref * nfb; in xgene_clk_pll_recalc_rate()
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| /drivers/clk/pistachio/ |
| A D | clk-pll.c | 129 pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref, in pll_get_params() argument
135 if (pll->rates[i].fref == fref && pll->rates[i].fout == fout) in pll_get_params()
149 if (i > 0 && pll->rates[i].fref == *parent_rate && in pll_round_rate()
210 vco = params->fref; in pll_gf40lp_frac_set_rate()
218 val = div64_u64(params->fref, params->refdiv); in pll_gf40lp_frac_set_rate()
366 vco = div_u64(params->fref * params->fbdiv, params->refdiv); in pll_gf40lp_laint_set_rate()
371 val = div_u64(params->fref, params->refdiv); in pll_gf40lp_laint_set_rate()
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| A D | clk.h | 95 unsigned long long fref; member
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| /drivers/clk/imx/ |
| A D | clk-imx31.c | 53 static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref) in _mx31_clocks_init() argument
56 clk[ckih] = imx_clk_fixed("ckih", fref); in _mx31_clocks_init()
127 u32 fref = 26000000; /* default */ in mx31_clocks_init_dt() local
134 if (!of_property_read_u32(osc_np, "clock-frequency", &fref)) { in mx31_clocks_init_dt()
144 _mx31_clocks_init(ccm, fref); in mx31_clocks_init_dt()
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| A D | clk-imx27.c | 51 static void __init _mx27_clocks_init(unsigned long fref) in _mx27_clocks_init() argument
56 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); in _mx27_clocks_init()
175 u32 fref = 26000000; /* default */ in mx27_clocks_init_dt() local
181 if (!of_property_read_u32(refnp, "clock-frequency", &fref)) { in mx27_clocks_init_dt()
189 _mx27_clocks_init(fref); in mx27_clocks_init_dt()
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| /drivers/phy/rockchip/ |
| A D | phy-rockchip-inno-dsidphy.c | 301 unsigned long fref, fout; in inno_dsidphy_pll_calc_rate() local
312 fref = prate / 2; in inno_dsidphy_pll_calc_rate()
319 min_prediv = DIV_ROUND_UP(fref, 40000000); in inno_dsidphy_pll_calc_rate()
320 max_prediv = fref / 5000000; in inno_dsidphy_pll_calc_rate()
327 do_div(tmp, fref); in inno_dsidphy_pll_calc_rate()
340 tmp = (u64)_fbdiv * fref; in inno_dsidphy_pll_calc_rate()
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| A D | phy-rockchip-samsung-hdptx.c | 904 const unsigned int fout = div_u64(rate, 200), fref = 24000; in rk_hdptx_phy_clk_pll_calc() local
921 mdiv = DIV_ROUND_UP(fvco, fref); in rk_hdptx_phy_clk_pll_calc()
925 if (fref * mdiv - fvco) { in rk_hdptx_phy_clk_pll_calc()
926 for (sdc = 264000; sdc <= 750000; sdc += fref) in rk_hdptx_phy_clk_pll_calc()
927 if (sdc * n > fref * mdiv) in rk_hdptx_phy_clk_pll_calc()
933 rational_best_approximation(fref * mdiv - fvco, in rk_hdptx_phy_clk_pll_calc()
939 rational_best_approximation(sdc * n - fref * mdiv, in rk_hdptx_phy_clk_pll_calc()
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| /drivers/tty/serial/8250/ |
| A D | 8250_lpss.c | 77 unsigned long fref = lpss->board->freq, fuart = baud * 16; in byt_set_termios() local
86 fuart *= rounddown_pow_of_two(fref / fuart); in byt_set_termios()
94 rational_best_approximation(fuart, fref, w, w, &m, &n); in byt_set_termios()
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| /drivers/gpu/drm/msm/dsi/phy/ |
| A D | dsi_phy_14nm.c | 212 u64 fref = VCO_REF_CLK_RATE; in pll_14nm_dec_frac_calc() local
214 DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref); in pll_14nm_dec_frac_calc()
216 dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref); in pll_14nm_dec_frac_calc()
255 u64 fref = VCO_REF_CLK_RATE; in pll_14nm_calc_vco_count() local
261 data = fref * vco_measure_time; in pll_14nm_calc_vco_count()
272 data = fref * kvco_measure_time; in pll_14nm_calc_vco_count()
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| A D | dsi_phy_10nm.c | 117 u64 fref = VCO_REF_CLK_RATE; in dsi_pll_calc_dec_frac() local
126 divider = fref * 2; in dsi_pll_calc_dec_frac()
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| A D | dsi_phy_7nm.c | 119 u64 fref = VCO_REF_CLK_RATE; in dsi_pll_calc_dec_frac() local
128 divider = fref * 2; in dsi_pll_calc_dec_frac()
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| /drivers/spi/ |
| A D | spi-pxa2xx.c | 802 unsigned long fref = xtal / 2; /* mandatory division by 2, in quark_x1000_get_clk_div() local
805 unsigned long fref1 = fref / 2; /* case 1 */ in quark_x1000_get_clk_div()
806 unsigned long fref2 = fref * 2 / 5; /* case 2 */ in quark_x1000_get_clk_div()
863 if (fref / rate >= 80) { in quark_x1000_get_clk_div()
868 q1 = DIV_ROUND_UP(fref, rate); in quark_x1000_get_clk_div()
872 fssp = (u64)fref * m; in quark_x1000_get_clk_div()
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| /drivers/video/fbdev/ |
| A D | tdfxfb.c | 291 int fref = 14318; in do_calc_pll() local
302 int n_estimated = ((freq * (m + 2) << k) / fref) - 2; in do_calc_pll()
312 int f = (fref * (n + 2) / (m + 2)) >> k; in do_calc_pll()
332 *freq_out = (fref * (n + 2) / (m + 2)) >> k; in do_calc_pll()
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| /drivers/gpu/drm/vc4/ |
| A D | vc4_hdmi_phy.c | 251 unsigned long long fref = OSCILLATOR_FREQUENCY; in phy_get_rm_offset() local
257 do_div(offset, fref); in phy_get_rm_offset()
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| /drivers/net/wireless/ti/wl12xx/ |
| A D | main.c | 1951 module_param_named(fref, fref_param, charp, 0);
1952 MODULE_PARM_DESC(fref, "FREF clock: 19.2, 26, 26x, 38.4, 38.4x, 52");
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