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Searched refs:fuse (Results 1 – 25 of 33) sorted by relevance

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/drivers/soc/tegra/fuse/
A Dfuse-tegra20.c56 fuse->apbdma.config.src_addr = fuse->phys + FUSE_BEGIN + offset; in tegra20_fuse_read()
58 err = dmaengine_slave_config(fuse->apbdma.chan, &fuse->apbdma.config); in tegra20_fuse_read()
102 fuse->apbdma.chan = NULL; in tegra20_fuse_release_channel()
109 dma_free_coherent(fuse->dev, sizeof(u32), fuse->apbdma.virt, in tegra20_fuse_free_coherent()
110 fuse->apbdma.phys); in tegra20_fuse_free_coherent()
112 fuse->apbdma.phys = 0x0; in tegra20_fuse_free_coherent()
124 if (!fuse->apbdma.chan) in tegra20_fuse_probe()
128 fuse); in tegra20_fuse_probe()
132 fuse->apbdma.virt = dma_alloc_coherent(fuse->dev, sizeof(u32), in tegra20_fuse_probe()
135 if (!fuse->apbdma.virt) in tegra20_fuse_probe()
[all …]
A Dfuse-tegra.c107 buffer[i] = fuse->read(fuse, offset + i * 4); in tegra_fuse_read()
130 fuse->lookups = kmemdup_array(fuse->soc->lookups, fuse->soc->num_lookups, in tegra_fuse_add_lookups()
135 nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups); in tegra_fuse_add_lookups()
184 fuse->soc->init(fuse); in tegra_fuse_probe()
205 err = fuse->soc->probe(fuse); in tegra_fuse_probe()
338 return fuse->read_early(fuse, offset) & 1; in tegra_fuse_read_spare()
343 return fuse->read_early(fuse, offset); in tegra_fuse_read_early()
348 if (!fuse->dev) in tegra_fuse_readl()
354 if (is_of_node(dev_fwnode(fuse->dev)) && !fuse->clk) in tegra_fuse_readl()
363 *value = fuse->read(fuse, offset); in tegra_fuse_readl()
[all …]
A Dfuse-tegra30.c45 if (WARN_ON(!fuse->base)) in tegra30_fuse_read_early()
48 return readl_relaxed(fuse->base + FUSE_BEGIN + offset); in tegra30_fuse_read_early()
51 static u32 tegra30_fuse_read(struct tegra_fuse *fuse, unsigned int offset) in tegra30_fuse_read() argument
56 err = pm_runtime_resume_and_get(fuse->dev); in tegra30_fuse_read()
60 value = readl_relaxed(fuse->base + FUSE_BEGIN + offset); in tegra30_fuse_read()
62 pm_runtime_put(fuse->dev); in tegra30_fuse_read()
89 static void __init tegra30_fuse_init(struct tegra_fuse *fuse) in tegra30_fuse_init() argument
91 fuse->read_early = tegra30_fuse_read_early; in tegra30_fuse_init()
92 fuse->read = tegra30_fuse_read; in tegra30_fuse_init()
96 if (fuse->soc->speedo_init) in tegra30_fuse_init()
[all …]
A Dfuse.h21 u32 (*read)(struct tegra_fuse *fuse, unsigned int offset);
27 void (*init)(struct tegra_fuse *fuse);
29 int (*probe)(struct tegra_fuse *fuse);
52 u32 (*read_early)(struct tegra_fuse *fuse, unsigned int offset);
53 u32 (*read)(struct tegra_fuse *fuse, unsigned int offset);
A DMakefile2 obj-y += fuse-tegra.o
3 obj-y += fuse-tegra30.o
5 obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += fuse-tegra20.o
/drivers/nvmem/
A Drcar-efuse.c33 struct rcar_fuse *fuse = priv; in rcar_fuse_reg_read() local
42 pm_runtime_put(fuse->dev); in rcar_fuse_reg_read()
63 struct rcar_fuse *fuse; in rcar_fuse_probe() local
71 fuse = devm_kzalloc(dev, sizeof(*fuse), GFP_KERNEL); in rcar_fuse_probe()
72 if (!fuse) in rcar_fuse_probe()
77 if (IS_ERR(fuse->base)) in rcar_fuse_probe()
78 return PTR_ERR(fuse->base); in rcar_fuse_probe()
80 fuse->dev = dev; in rcar_fuse_probe()
81 fuse->keepouts[0].start = 0; in rcar_fuse_probe()
89 config.priv = fuse; in rcar_fuse_probe()
[all …]
/drivers/pmdomain/qcom/
A Dcpr.c808 for (; fuse < end; fuse++, fuses++) { in cpr_populate_ring_osc_idx()
867 for (i = 0; fuse <= end; fuse++, fuses++, i++, fdata++) { in cpr_fuse_corner_init()
884 fuse->uV = clamp(uV, fuse->min_uV, fuse->max_uV); in cpr_fuse_corner_init()
904 fuse->step_quot = desc->step_quot[fuse->ring_osc_idx]; in cpr_fuse_corner_init()
916 for (fuse = drv->fuse_corners, i = 0; fuse <= end; fuse++, i++) { in cpr_fuse_corner_init()
917 if (fuse->uV > fuse->max_uV) in cpr_fuse_corner_init()
918 fuse->uV = fuse->max_uV; in cpr_fuse_corner_init()
919 else if (fuse->uV < fuse->min_uV) in cpr_fuse_corner_init()
920 fuse->uV = fuse->min_uV; in cpr_fuse_corner_init()
944 i, fuse->min_uV, fuse->uV, fuse->max_uV, in cpr_fuse_corner_init()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/
A Dbase.c27 nvkm_fuse_read(struct nvkm_fuse *fuse, u32 addr) in nvkm_fuse_read() argument
29 return fuse->func->read(fuse, addr); in nvkm_fuse_read()
47 struct nvkm_fuse *fuse; in nvkm_fuse_new_() local
48 if (!(fuse = *pfuse = kzalloc(sizeof(*fuse), GFP_KERNEL))) in nvkm_fuse_new_()
50 nvkm_subdev_ctor(&nvkm_fuse, device, type, inst, &fuse->subdev); in nvkm_fuse_new_()
51 fuse->func = func; in nvkm_fuse_new_()
52 spin_lock_init(&fuse->lock); in nvkm_fuse_new_()
A DKbuild2 nvkm-y += nvkm/subdev/fuse/base.o
3 nvkm-y += nvkm/subdev/fuse/nv50.o
4 nvkm-y += nvkm/subdev/fuse/gf100.o
5 nvkm-y += nvkm/subdev/fuse/gm107.o
A Dnv50.c27 nv50_fuse_read(struct nvkm_fuse *fuse, u32 addr) in nv50_fuse_read() argument
29 struct nvkm_device *device = fuse->subdev.device; in nv50_fuse_read()
34 spin_lock_irqsave(&fuse->lock, flags); in nv50_fuse_read()
38 spin_unlock_irqrestore(&fuse->lock, flags); in nv50_fuse_read()
A Dgf100.c27 gf100_fuse_read(struct nvkm_fuse *fuse, u32 addr) in gf100_fuse_read() argument
29 struct nvkm_device *device = fuse->subdev.device; in gf100_fuse_read()
34 spin_lock_irqsave(&fuse->lock, flags); in gf100_fuse_read()
40 spin_unlock_irqrestore(&fuse->lock, flags); in gf100_fuse_read()
A Dgm107.c29 gm107_fuse_read(struct nvkm_fuse *fuse, u32 addr) in gm107_fuse_read() argument
31 struct nvkm_device *device = fuse->subdev.device; in gm107_fuse_read()
/drivers/media/platform/amphion/
A Dvpu_imx8q.c228 u32 fuse = vpu_imx8q_get_fuse(); in vpu_imx8q_check_codec() local
231 if (fuse & VPU_ENCODER_MASK) in vpu_imx8q_check_codec()
234 fuse >>= VPU_IMX_DECODER_FUSE_OFFSET; in vpu_imx8q_check_codec()
235 fuse &= VPU_DECODER_MASK; in vpu_imx8q_check_codec()
237 if (fuse == VPU_DECODER_MASK) in vpu_imx8q_check_codec()
245 u32 fuse = vpu_imx8q_get_fuse(); in vpu_imx8q_check_fmt() local
248 fuse >>= VPU_IMX_DECODER_FUSE_OFFSET; in vpu_imx8q_check_fmt()
249 fuse &= VPU_DECODER_MASK; in vpu_imx8q_check_fmt()
251 if (fuse == VPU_DECODER_HEVC_MASK && pixelfmt == V4L2_PIX_FMT_HEVC) in vpu_imx8q_check_fmt()
253 if (fuse == VPU_DECODER_H264_MASK && pixelfmt == V4L2_PIX_FMT_H264) in vpu_imx8q_check_fmt()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/volt/
A Dgf117.c32 struct nvkm_fuse *fuse = device->fuse; in gf117_volt_speedo_read() local
34 if (!fuse) in gf117_volt_speedo_read()
37 return nvkm_fuse_read(fuse, 0x3a8); in gf117_volt_speedo_read()
A Dgf100.c32 struct nvkm_fuse *fuse = device->fuse; in gf100_volt_speedo_read() local
34 if (!fuse) in gf100_volt_speedo_read()
37 return nvkm_fuse_read(fuse, 0x1cc); in gf100_volt_speedo_read()
A Dgk104.c72 struct nvkm_fuse *fuse = device->fuse; in gk104_volt_speedo_read() local
75 if (!fuse) in gk104_volt_speedo_read()
79 ret = nvkm_fuse_read(fuse, 0x3a8); in gk104_volt_speedo_read()
/drivers/gpu/drm/nouveau/nvkm/engine/device/
A Dbase.c785 .fuse = { 0x00000001, nv50_fuse_new },
888 .fuse = { 0x00000001, nv50_fuse_new },
919 .fuse = { 0x00000001, nv50_fuse_new },
950 .fuse = { 0x00000001, nv50_fuse_new },
981 .fuse = { 0x00000001, nv50_fuse_new },
1012 .fuse = { 0x00000001, nv50_fuse_new },
1043 .fuse = { 0x00000001, nv50_fuse_new },
1074 .fuse = { 0x00000001, nv50_fuse_new },
1105 .fuse = { 0x00000001, nv50_fuse_new },
1138 .fuse = { 0x00000001, nv50_fuse_new },
[all …]
/drivers/gpu/drm/i915/gt/
A Dintel_sseu.c330 u32 fuse; in cherryview_sseu_info_init() local
332 fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT); in cherryview_sseu_info_init()
337 if (!(fuse & CHV_FGT_DISABLE_SS0)) { in cherryview_sseu_info_init()
339 REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R0_MASK, fuse) | in cherryview_sseu_info_init()
340 REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS0_R0_MASK); in cherryview_sseu_info_init()
346 if (!(fuse & CHV_FGT_DISABLE_SS1)) { in cherryview_sseu_info_init()
348 REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R0_MASK, fuse) | in cherryview_sseu_info_init()
349 REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS1_R0_MASK); in cherryview_sseu_info_init()
A Dintel_gt_mcr.c111 unsigned long fuse; in intel_gt_mcr_init() local
137 fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK, in intel_gt_mcr_init()
141 fuse = REG_FIELD_GET(GT_L3_EXC_MASK, in intel_gt_mcr_init()
148 for_each_set_bit(i, &fuse, 3) in intel_gt_mcr_init()
/drivers/phy/tegra/
A Dxusb-tegra124.c216 struct tegra124_xusb_fuse_calibration fuse; member
503 value |= (priv->fuse.hs_squelch_level << in tegra124_usb2_phy_power_on()
526 value |= (priv->fuse.hs_curr_level[index] + in tegra124_usb2_phy_power_on()
543 value |= (priv->fuse.hs_term_range_adj << in tegra124_usb2_phy_power_on()
545 (priv->fuse.hs_iref_cap << in tegra124_usb2_phy_power_on()
1671 for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) { in tegra124_xusb_read_fuse_calibration()
1672 fuse->hs_curr_level[i] = in tegra124_xusb_read_fuse_calibration()
1676 fuse->hs_iref_cap = in tegra124_xusb_read_fuse_calibration()
1679 fuse->hs_term_range_adj = in tegra124_xusb_read_fuse_calibration()
1682 fuse->hs_squelch_level = in tegra124_xusb_read_fuse_calibration()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
A Dg84.c34 if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) in g84_temp_get()
46 if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) { in g84_sensor_setup()
/drivers/net/wireless/ti/wl18xx/
A Dmain.c1394 u32 fuse; in wl18xx_get_pg_ver() local
1402 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse); in wl18xx_get_pg_ver()
1406 package_type = (fuse >> WL18XX_PACKAGE_TYPE_OFFSET) & 1; in wl18xx_get_pg_ver()
1408 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse); in wl18xx_get_pg_ver()
1412 pg_ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET; in wl18xx_get_pg_ver()
1413 rom = (fuse & WL18XX_ROM_VER_MASK) >> WL18XX_ROM_VER_OFFSET; in wl18xx_get_pg_ver()
1416 metal = (fuse & WL18XX_METAL_VER_MASK) >> in wl18xx_get_pg_ver()
1419 metal = (fuse & WL18XX_NEW_METAL_VER_MASK) >> in wl18xx_get_pg_ver()
1422 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse); in wl18xx_get_pg_ver()
1426 rdl_ver = (fuse & WL18XX_RDL_VER_MASK) >> WL18XX_RDL_VER_OFFSET; in wl18xx_get_pg_ver()
/drivers/soc/tegra/
A DMakefile2 obj-y += fuse/
/drivers/accel/ivpu/
A Divpu_hw_btrs.c134 u32 fuse; in read_tile_config_fuse() local
137 fuse = REGB_RD32(VPU_HW_BTRS_LNL_TILE_FUSE); in read_tile_config_fuse()
138 if (!REG_TEST_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, VALID, fuse)) { in read_tile_config_fuse()
139 ivpu_err(vdev, "Fuse: invalid (0x%x)\n", fuse); in read_tile_config_fuse()
143 config = REG_GET_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, CONFIG, fuse); in read_tile_config_fuse()
/drivers/thermal/tegra/
A DMakefile6 tegra-soctherm-y := soctherm.o soctherm-fuse.o

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