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Searched refs:fw_based_mclk_switching (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c872 if (new_clocks->fw_based_mclk_switching != clk_mgr_base->clks.fw_based_mclk_switching && in dcn401_build_update_bandwidth_clocks_sequence()
873 new_clocks->fw_based_mclk_switching) { in dcn401_build_update_bandwidth_clocks_sequence()
875 clk_mgr_base->clks.fw_based_mclk_switching = new_clocks->fw_based_mclk_switching; in dcn401_build_update_bandwidth_clocks_sequence()
877 …_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching; in dcn401_build_update_bandwidth_clocks_sequence()
881 ….params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching; in dcn401_build_update_bandwidth_clocks_sequence()
1048 if (new_clocks->fw_based_mclk_switching != clk_mgr_base->clks.fw_based_mclk_switching && in dcn401_build_update_bandwidth_clocks_sequence()
1049 safe_to_lower && !new_clocks->fw_based_mclk_switching) { in dcn401_build_update_bandwidth_clocks_sequence()
1051 clk_mgr_base->clks.fw_based_mclk_switching = new_clocks->fw_based_mclk_switching; in dcn401_build_update_bandwidth_clocks_sequence()
1053 …_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching; in dcn401_build_update_bandwidth_clocks_sequence()
1057 ….params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching; in dcn401_build_update_bandwidth_clocks_sequence()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c295 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || in dcn30_fpu_update_soc_for_wm_a()
318 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dcn30_fpu_calculate_wm_and_dlg()
329 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = in dcn30_fpu_calculate_wm_and_dlg()
332 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn30_fpu_calculate_wm_and_dlg()
423 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn30_fpu_calculate_wm_and_dlg()
498 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && in dcn30_fpu_calculate_wm_and_dlg()
518 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) in dcn30_fpu_calculate_wm_and_dlg()
/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_hwseq.c1168 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) && in dcn30_hardware_release()
1189 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switchi… in dcn30_prepare_bandwidth()
1201 if (!dc->clk_mgr->clks.fw_based_mclk_switching) in dcn30_prepare_bandwidth()
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c1793 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switchin… in dcn32_prepare_bandwidth()
1805 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) in dcn32_prepare_bandwidth()
1808 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switchin… in dcn32_prepare_bandwidth()
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c1672 …xt->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; in dcn32_calculate_dlg_params()
2355 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dcn32_calculate_wm_and_dlg_fpu()
2372 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true; in dcn32_calculate_wm_and_dlg_fpu()
2375 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn32_calculate_wm_and_dlg_fpu()
2407 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dcn32_calculate_wm_and_dlg_fpu()
2504 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn32_calculate_wm_and_dlg_fpu()
2523 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !subvp_in_use) { in dcn32_calculate_wm_and_dlg_fpu()
3603 if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) && in dcn32_override_min_req_memclk()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_utils.c510 …context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = context->bw_ctx.bw.dcn.fams2_global_config.fe… in dml21_build_fams2_programming()
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c2451 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn20_optimize_bandwidth()
2455 dc->clk_mgr->clks.fw_based_mclk_switching = true; in dcn20_optimize_bandwidth()
2457 dc->clk_mgr->clks.fw_based_mclk_switching = false; in dcn20_optimize_bandwidth()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.c729 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) in dcn32_update_clocks()
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_hw_sequencer.c649 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in set_p_state_switch_method()
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.c1759 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dml1_validate()
2015 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use) in dcn32_populate_dml_pipes_from_context()
/drivers/gpu/drm/amd/display/dc/
A Ddc.h685 bool fw_based_mclk_switching; member
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c1171 …xt->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; in dcn20_calculate_dlg_params()

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