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Searched refs:gate_clks (Results 1 – 24 of 24) sorted by relevance

/drivers/clk/samsung/
A Dclk-exynos7.c192 .gate_clks = topc_gate_clks,
384 .gate_clks = top0_gate_clks,
566 .gate_clks = top1_gate_clks,
613 .gate_clks = ccore_gate_clks,
680 .gate_clks = peric0_gate_clks,
804 .gate_clks = peric1_gate_clks,
859 .gate_clks = peris_gate_clks,
969 .gate_clks = fsys0_gate_clks,
1100 .gate_clks = fsys1_gate_clks,
1213 .gate_clks = mscl_gate_clks,
[all …]
A Dclk-exynosautov9.c954 .gate_clks = top_gate_clks,
1014 .gate_clks = busmc_gate_clks,
1072 .gate_clks = core_gate_clks,
1151 .gate_clks = dpum_gate_clks,
1391 .gate_clks = fsys0_gate_clks,
1518 .gate_clks = fsys1_gate_clks,
1585 .gate_clks = fsys2_gate_clks,
1840 .gate_clks = peric0_gate_clks,
2095 .gate_clks = peric1_gate_clks,
2142 .gate_clks = peris_gate_clks,
A Dclk-exynos5260.c148 .gate_clks = aud_gate_clks,
338 .gate_clks = disp_gate_clks,
502 .gate_clks = fsys_gate_clks,
593 .gate_clks = g2d_gate_clks,
656 .gate_clks = g3d_gate_clks,
789 .gate_clks = gscl_gate_clks,
908 .gate_clks = isp_gate_clks,
1028 .gate_clks = mfc_gate_clks,
1177 .gate_clks = mif_gate_clks,
1383 .gate_clks = peri_gate_clks,
[all …]
A Dclk-exynos850.c570 .gate_clks = top_gate_clks,
708 .gate_clks = apm_gate_clks,
991 .gate_clks = aud_gate_clks,
1094 .gate_clks = cmgp_gate_clks,
1296 .gate_clks = cpucl0_gate_clks,
1559 .gate_clks = g3d_gate_clks,
1661 .gate_clks = hsi_gate_clks,
1793 .gate_clks = is_gate_clks,
2083 .gate_clks = peri_gate_clks,
2198 .gate_clks = core_gate_clks,
[all …]
A Dclk-exynos5-subcmu.c67 exynos5_subcmu_defer_gate(ctx, (*_cmu)->gate_clks, in exynos5_subcmus_init()
111 samsung_clk_register_gate(ctx, info->gate_clks, info->nr_gate_clks); in exynos5_subcmu_probe()
A Dclk-exynos7885.c350 .gate_clks = top_gate_clks,
569 .gate_clks = peri_gate_clks,
678 .gate_clks = core_gate_clks,
803 .gate_clks = fsys_gate_clks,
A Dclk-exynos7870.c731 .gate_clks = mif_gate_clks,
1009 .gate_clks = dispaud_gate_clks,
1130 .gate_clks = fsys_gate_clks,
1246 .gate_clks = g3d_gate_clks,
1433 .gate_clks = isp_gate_clks,
1522 .gate_clks = mfcmscl_gate_clks,
1772 .gate_clks = peri_gate_clks,
A Dclk-exynos5-subcmu.h16 const struct samsung_gate_clock *gate_clks; member
A Dclk-exynos5433.c816 .gate_clks = top_gate_clks,
899 .gate_clks = cpif_gate_clks,
1551 .gate_clks = mif_gate_clks,
2356 .gate_clks = fsys_gate_clks,
2481 .gate_clks = g2d_gate_clks,
2905 .gate_clks = disp_gate_clks,
3077 .gate_clks = aud_gate_clks,
3362 .gate_clks = g3d_gate_clks,
3505 .gate_clks = gscl_gate_clks,
4240 .gate_clks = mfc_gate_clks,
[all …]
A Dclk-exynos3250.c432 static const struct samsung_gate_clock gate_clks[] __initconst = { variable
807 .gate_clks = gate_clks,
808 .nr_gate_clks = ARRAY_SIZE(gate_clks),
1071 .gate_clks = isp_gate_clks,
A Dclk-fsd.c310 .gate_clks = cmu_gate_clks,
673 .gate_clks = peric_gate_clks,
972 .gate_clks = fsys0_gate_clks,
1144 .gate_clks = fsys1_gate_clks,
1423 .gate_clks = imem_gate_clks,
1548 .gate_clks = mfc_gate_clks,
1752 .gate_clks = cam_csi_gate_clks,
A Dclk-exynos5420.c1333 .gate_clks = exynos5x_disp_gate_clks,
1343 .gate_clks = exynos5x_gsc_gate_clks,
1351 .gate_clks = exynos5x_g3d_gate_clks,
1361 .gate_clks = exynos5x_mfc_gate_clks,
1371 .gate_clks = exynos5x_mscl_gate_clks,
1379 .gate_clks = exynos5800_mau_gate_clks,
A Dclk-s5pv210.c545 static const struct samsung_gate_clock gate_clks[] __initconst = { variable
777 samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks)); in __s5pv210_clk_init()
A Dclk.c343 if (cmu->gate_clks) in samsung_cmu_register_clocks()
344 samsung_clk_register_gate(ctx, cmu->gate_clks, in samsung_cmu_register_clocks()
A Dclk-exynos8895.c1297 .gate_clks = top_gate_clks,
1531 .gate_clks = peris_gate_clks,
1821 .gate_clks = fsys0_gate_clks,
2120 .gate_clks = fsys1_gate_clks,
2309 .gate_clks = peric0_gate_clks,
2754 .gate_clks = peric1_gate_clks,
A Dclk-exynos990.c1129 .gate_clks = top_gate_clks,
1302 .gate_clks = hsi0_gate_clks,
1470 .gate_clks = peris_gate_clks,
A Dclk-gs101.c1431 .gate_clks = cmu_top_gate_clks,
1908 .gate_clks = apm_gate_clks,
2371 .gate_clks = hsi0_gate_clks,
2861 .gate_clks = hsi2_gate_clks,
3421 .gate_clks = misc_gate_clks,
4018 .gate_clks = peric0_gate_clks,
4366 .gate_clks = peric1_gate_clks,
A Dclk-exynos5410.c262 .gate_clks = exynos5410_gate_clks,
A Dclk.h350 const struct samsung_gate_clock *gate_clks; member
A Dclk-exynos4.c1277 .gate_clks = exynos4_gate_clks,
1290 .gate_clks = exynos4210_gate_clks,
1305 .gate_clks = exynos4x12_gate_clks,
A Dclk-exynos5250.c681 .gate_clks = exynos5250_disp_gate_clks,
/drivers/clk/sophgo/
A Dclk-sg2042-rpgate.c194 const struct sg2042_rpgate_clock gate_clks[], in sg2042_clk_register_rpgates() argument
202 gate = &gate_clks[i]; in sg2042_clk_register_rpgates()
A Dclk-sg2042-clkgen.c849 const struct sg2042_gate_clock gate_clks[], in sg2042_clk_register_gates() argument
857 gate = &gate_clks[i]; in sg2042_clk_register_gates()
894 const struct sg2042_gate_clock gate_clks[], in sg2042_clk_register_gates_fw() argument
902 gate = &gate_clks[i]; in sg2042_clk_register_gates_fw()
/drivers/clk/tegra/
A Dclk-tegra-periph.c772 static struct tegra_periph_init_data gate_clks[] = { variable
894 for (i = 0; i < ARRAY_SIZE(gate_clks); i++) { in gate_clk_init()
897 data = gate_clks + i; in gate_clk_init()

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