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Searched refs:get_wptr (Results 1 – 25 of 70) sorted by relevance

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/drivers/gpu/drm/radeon/
A Dradeon_asic.c193 .get_wptr = &r100_gfx_get_wptr,
343 .get_wptr = &r100_gfx_get_wptr,
357 .get_wptr = &r100_gfx_get_wptr,
914 .get_wptr = &r600_gfx_get_wptr,
927 .get_wptr = &r600_dma_get_wptr,
1012 .get_wptr = &uvd_v1_0_get_wptr,
1211 .get_wptr = &uvd_v1_0_get_wptr,
1318 .get_wptr = &r600_gfx_get_wptr,
1331 .get_wptr = &r600_dma_get_wptr,
1656 .get_wptr = &uvd_v1_0_get_wptr,
[all …]
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_ih.h88 u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); member
96 #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih))
A Damdgpu_ring.h218 u64 (*get_wptr)(struct amdgpu_ring *ring); member
418 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
A Djpeg_v2_5.c697 .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
728 .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
A Dcik_ih.c434 .get_wptr = cik_ih_get_wptr,
A Dsi_ih.c296 .get_wptr = si_ih_get_wptr,
A Diceland_ih.c424 .get_wptr = iceland_ih_get_wptr,
A Dcz_ih.c432 .get_wptr = cz_ih_get_wptr,
A Dvce_v3_0.c923 .get_wptr = vce_v3_0_ring_get_wptr,
947 .get_wptr = vce_v3_0_ring_get_wptr,
A Duvd_v6_0.c1554 .get_wptr = uvd_v6_0_ring_get_wptr,
1580 .get_wptr = uvd_v6_0_ring_get_wptr,
1609 .get_wptr = uvd_v6_0_enc_ring_get_wptr,
A Dtonga_ih.c483 .get_wptr = tonga_ih_get_wptr,
A Dvce_v2_0.c640 .get_wptr = vce_v2_0_ring_get_wptr,
A Djpeg_v3_0.c598 .get_wptr = jpeg_v3_0_dec_ring_get_wptr,
A Djpeg_v5_0_0.c684 .get_wptr = jpeg_v5_0_0_dec_ring_get_wptr,
A Damdgpu_umsch_mm.c99 .get_wptr = umsch_mm_ring_get_wptr,
A Duvd_v3_1.c185 .get_wptr = uvd_v3_1_ring_get_wptr,
A Duvd_v4_2.c779 .get_wptr = uvd_v4_2_ring_get_wptr,
A Dvega10_ih.c641 .get_wptr = vega10_ih_get_wptr,
A Djpeg_v1_0.c562 .get_wptr = jpeg_v1_0_decode_ring_get_wptr,
A Duvd_v5_0.c886 .get_wptr = uvd_v5_0_ring_get_wptr,
A Dvega20_ih.c738 .get_wptr = vega20_ih_get_wptr,
/drivers/gpu/drm/msm/adreno/
A Da5xx_preempt.c49 wptr = get_wptr(ring); in update_wptr()
68 empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); in get_next_ring()
149 a5xx_gpu->preempt[ring->id]->wptr = get_wptr(ring); in a5xx_preempt_trigger()
A Da6xx_preempt.c52 wptr = get_wptr(ring); in update_wptr()
76 empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); in get_next_ring()
289 record_ptr->wptr = get_wptr(ring); in a6xx_preempt_trigger()
A Dadreno_gpu.c737 wptr = get_wptr(ring); in adreno_flush()
748 uint32_t wptr = get_wptr(ring); in adreno_idle()
779 state->ring[i].wptr = get_wptr(gpu->rb[i]); in adreno_gpu_state_get()
1054 printk("rb wptr: %d\n", get_wptr(ring)); in adreno_dump_info()
A Dadreno_gpu.h681 static inline uint32_t get_wptr(struct msm_ringbuffer *ring) in get_wptr() function

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