| /drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| A D | gv100.c | 121 u32 gpc; in gv100_gr_scg_estimate_perf() local
135 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gv100_gr_scg_estimate_perf()
153 max_tpc_gpc = num_tpc_gpc[gpc] > max_tpc_gpc ? num_tpc_gpc[gpc] : max_tpc_gpc; in gv100_gr_scg_estimate_perf()
160 scg_gpc_pix_perf = scale_factor * num_tpc_gpc[gpc] / gr->tpc_nr[gpc]; in gv100_gr_scg_estimate_perf()
167 num_tpc_mask = gr->ppc_tpc_mask[gpc][pes] & gpc_tpc_mask[gpc]; in gv100_gr_scg_estimate_perf()
194 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gv100_gr_scg_estimate_perf()
231 u32 gpc, tpc, pes, gtpc; in gv100_gr_oneinit_sm_id() local
242 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gv100_gr_oneinit_sm_id()
244 gpc_tpc_mask[gpc] |= gr->ppc_tpc_mask[gpc][pes]; in gv100_gr_oneinit_sm_id()
248 for (maxperf = -1, gpc = 0; gpc < gr->gpc_nr; gpc++) { in gv100_gr_oneinit_sm_id()
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| A D | ctxgp100.c | 52 int gpc, ppc, n = 0; in gp100_grctx_generate_attrib() local
58 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp100_grctx_generate_attrib()
60 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
63 const u32 o = PPC_UNIT(gpc, ppc, 0); in gp100_grctx_generate_attrib()
65 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gp100_grctx_generate_attrib()
74 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
97 int gpc; in gp100_grctx_generate_attrib_cb_size() local
99 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gp100_grctx_generate_attrib_cb_size()
114 const u8 gpc = gr->sm[sm].gpc; in gp100_grctx_generate_smid_config() local
116 dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8); in gp100_grctx_generate_smid_config()
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| A D | ctxgf100.c | 1037 int gpc, tpc; in gf100_grctx_generate_attrib() local
1042 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_attrib()
1253 int i, gpc; in gf100_grctx_generate_alpha_beta_tables() local
1265 for (gpc = 0; atarget && gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_alpha_beta_tables()
1266 if (abits[gpc] < gr->tpc_nr[gpc]) { in gf100_grctx_generate_alpha_beta_tables()
1273 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_alpha_beta_tables()
1274 u32 bbits = gr->tpc_nr[gpc] - abits[gpc]; in gf100_grctx_generate_alpha_beta_tables()
1275 amask |= ((1 << abits[gpc]) - 1) << (gpc * 8); in gf100_grctx_generate_alpha_beta_tables()
1276 bmask |= ((1 << bbits) - 1) << abits[gpc] << (gpc * 8); in gf100_grctx_generate_alpha_beta_tables()
1288 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]); in gf100_grctx_generate_tpc_nr()
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| A D | ctxgp102.c | 51 int gpc, ppc, n = 0; in gp102_grctx_generate_attrib() local
57 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp102_grctx_generate_attrib()
59 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
63 const u32 o = PPC_UNIT(gpc, ppc, 0); in gp102_grctx_generate_attrib()
64 const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4)); in gp102_grctx_generate_attrib()
66 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gp102_grctx_generate_attrib()
76 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
90 int gpc; in gp102_grctx_generate_attrib_cb_size() local
92 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gp102_grctx_generate_attrib_cb_size()
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| A D | ctxgm200.c | 55 const u8 gpc = gr->sm[sm].gpc; in gm200_grctx_generate_smid_config() local
57 dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8); in gm200_grctx_generate_smid_config()
58 gpcs[gpc] |= sm << (tpc * 8); in gm200_grctx_generate_smid_config()
87 int gpc, ppc, i; in gm200_grctx_generate_dist_skip_table() local
89 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gm200_grctx_generate_dist_skip_table()
91 u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
92 u8 ppc_tpcm = gr->ppc_tpc_mask[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
95 ppc_tpcm ^= gr->ppc_tpc_mask[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
96 ((u8 *)data)[gpc] |= ppc_tpcm; in gm200_grctx_generate_dist_skip_table()
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| A D | ctxgm107.c | 909 int gpc, ppc, n = 0; in gm107_grctx_generate_attrib() local
914 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gm107_grctx_generate_attrib()
916 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
917 const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
919 const u32 o = PPC_UNIT(gpc, ppc, 0); in gm107_grctx_generate_attrib()
921 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gm107_grctx_generate_attrib()
926 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
929 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
953 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), sm); in gm107_grctx_generate_sm_id()
954 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm); in gm107_grctx_generate_sm_id()
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| A D | gf100.c | 1416 int rop, gpc; in gf100_gr_trap_intr() local
1504 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { in gf100_gr_trap_intr()
1559 u32 gpc; in gf100_gr_ctxctl_debug() local
1562 for (gpc = 0; gpc < gpcnr; gpc++) in gf100_gr_ctxctl_debug()
1898 int tpc, gpc; in gf100_gr_oneinit_sm_id() local
1901 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_gr_oneinit_sm_id()
1903 gr->sm[gr->sm_nr].gpc = gpc; in gf100_gr_oneinit_sm_id()
2241 int gpc, tpc; in gf100_gr_init_419cc0() local
2245 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_gr_init_419cc0()
2304 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_gr_init_zcull()
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| A D | ctxgv100.c | 73 int gpc, ppc, n = 0; in gv100_grctx_generate_attrib() local
79 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gv100_grctx_generate_attrib()
81 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
85 const u32 o = PPC_UNIT(gpc, ppc, 0); in gv100_grctx_generate_attrib()
87 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gv100_grctx_generate_attrib()
96 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
160 gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) in gv100_grctx_generate_sm_id() argument
164 tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc); in gv100_grctx_generate_sm_id()
166 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); in gv100_grctx_generate_sm_id()
167 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm); in gv100_grctx_generate_sm_id()
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| A D | ctxgf117.c | 254 int gpc, ppc; in gf117_grctx_generate_attrib() local
259 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf117_grctx_generate_attrib()
261 const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
262 const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
264 const u32 o = PPC_UNIT(gpc, ppc, 0); in gf117_grctx_generate_attrib()
266 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gf117_grctx_generate_attrib()
270 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
272 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
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| A D | tu102.c | 45 int tpc = gv100_gr_nonpes_aware_tpc(gr, gr->sm[sm].gpc, gr->sm[sm].tpc); in tu102_gr_init_fs()
47 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + tpc * 4), sm); in tu102_gr_init_fs()
60 u8 bank[GPC_MAX] = {}, gpc, i, j; in tu102_gr_init_zcull() local
71 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in tu102_gr_init_zcull()
72 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in tu102_gr_init_zcull()
73 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); in tu102_gr_init_zcull()
74 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in tu102_gr_init_zcull()
76 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in tu102_gr_init_zcull()
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| A D | gf117.c | 131 u8 bank[GPC_MAX] = {}, gpc, i, j; in gf117_gr_init_zcull() local
142 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf117_gr_init_zcull()
143 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in gf117_gr_init_zcull()
144 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); in gf117_gr_init_zcull()
145 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in gf117_gr_init_zcull()
147 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in gf117_gr_init_zcull()
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| A D | ctxgk104.c | 925 int i, j, gpc, ppc; in gk104_grctx_generate_alpha_beta_tables() local
933 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gk104_grctx_generate_alpha_beta_tables()
935 u32 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
946 pmask = gr->ppc_tpc_mask[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
949 amask |= (u64)pmask << (gpc * 8); in gk104_grctx_generate_alpha_beta_tables()
951 pmask ^= gr->ppc_tpc_mask[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
952 bmask |= (u64)pmask << (gpc * 8); in gk104_grctx_generate_alpha_beta_tables()
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| A D | ctxgf108.c | 746 int gpc, tpc; in gf108_grctx_generate_attrib() local
751 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf108_grctx_generate_attrib()
752 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { in gf108_grctx_generate_attrib()
756 const u32 o = TPC_UNIT(gpc, tpc, 0x500); in gf108_grctx_generate_attrib()
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| A D | gp102.c | 89 u32 mask = 0, data, gpc; in gp102_gr_init_swdx_pes_mask() local
91 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp102_gr_init_swdx_pes_mask()
92 data = nvkm_rd32(device, GPC_UNIT(gpc, 0x0c50)) & 0x0000000f; in gp102_gr_init_swdx_pes_mask()
93 mask |= data << (gpc * 4); in gp102_gr_init_swdx_pes_mask()
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| A D | gk104.c | 418 int gpc, ppc; in gk104_gr_init_ppc_exceptions() local
420 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gk104_gr_init_ppc_exceptions()
422 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gk104_gr_init_ppc_exceptions()
424 nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); in gk104_gr_init_ppc_exceptions()
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| A D | ctxtu102.c | 34 tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) in tu102_grctx_generate_sm_id() argument
38 tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc); in tu102_grctx_generate_sm_id()
40 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); in tu102_grctx_generate_sm_id()
41 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm); in tu102_grctx_generate_sm_id()
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| A D | ctxga102.c | 25 ga102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) in ga102_grctx_generate_sm_id() argument
29 tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc); in ga102_grctx_generate_sm_id()
31 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); in ga102_grctx_generate_sm_id()
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| A D | gm107.c | 294 gm107_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) in gm107_gr_init_shader_exceptions() argument
297 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); in gm107_gr_init_shader_exceptions()
298 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); in gm107_gr_init_shader_exceptions()
302 gm107_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) in gm107_gr_init_504430() argument
305 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); in gm107_gr_init_504430()
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| A D | gf100.h | 127 u8 gpc; member
175 void (*init_tex_hww_esr)(struct gf100_gr *, int gpc, int tpc);
176 void (*init_504430)(struct gf100_gr *, int gpc, int tpc);
177 void (*init_shader_exceptions)(struct gf100_gr *, int gpc, int tpc);
182 void (*trap_mp)(struct gf100_gr *, int gpc, int tpc);
263 u32 gv100_gr_nonpes_aware_tpc(struct gf100_gr *gr, u32 gpc, u32 tpc);
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| A D | gp100.c | 72 gp100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) in gp100_gr_init_shader_exceptions() argument
75 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); in gp100_gr_init_shader_exceptions()
76 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000105); in gp100_gr_init_shader_exceptions()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/ |
| A D | gsp.c | 120 for (int gpc = 0; gpc < 32; gpc++) { in r570_gsp_get_static_info() local
121 if (gpc_mask & BIT(gpc)) { in r570_gsp_get_static_info()
122 ret = r570_gr_tpc_mask(gsp, gpc, &tpc_mask); in r570_gsp_get_static_info()
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| /drivers/gpu/drm/nouveau/ |
| A D | nouveau_svm.c | 62 u8 gpc; member
397 u64 inst, u8 hub, u8 gpc, u8 client) in nouveau_svm_fault_cancel() argument
399 SVM_DBG(svm, "cancel %016llx %d %02x %02x", inst, hub, gpc, client); in nouveau_svm_fault_cancel()
404 .gpc = gpc, in nouveau_svm_fault_cancel()
416 fault->gpc, in nouveau_svm_fault_cancel_fault()
466 const u8 gpc = (info & 0x1f000000) >> 24; in nouveau_svm_fault_cache() local
480 nouveau_svm_fault_cancel(svm, inst, hub, gpc, client); in nouveau_svm_fault_cache()
491 fault->gpc = gpc; in nouveau_svm_fault_cache()
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| /drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/ |
| A D | gpcgf100.fuc3 | 33 #include "gpc.fuc"
40 #include "gpc.fuc"
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| A D | gpcgk104.fuc3 | 33 #include "gpc.fuc"
40 #include "gpc.fuc"
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| A D | gpcgk110.fuc3 | 33 #include "gpc.fuc"
40 #include "gpc.fuc"
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