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Searched refs:gpu_addr (Results 1 – 25 of 183) sorted by relevance

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/drivers/gpu/drm/radeon/
A Dr600_dma.c150 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); in r600_dma_resume()
236 u64 gpu_addr; in r600_dma_ring_test() local
243 gpu_addr = rdev->wb.gpu_addr + index; in r600_dma_ring_test()
254 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in r600_dma_ring_test()
290 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_dma_fence_ring_emit()
317 u64 addr = semaphore->gpu_addr; in r600_dma_semaphore_ring_emit()
343 u64 gpu_addr; in r600_dma_ib_test() local
350 gpu_addr = rdev->wb.gpu_addr + index; in r600_dma_ib_test()
359 ib.ptr[1] = lower_32_bits(gpu_addr); in r600_dma_ib_test()
360 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in r600_dma_ib_test()
[all …]
A Dcik_sdma.c155 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
203 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_sdma_fence_ring_emit()
232 u64 addr = semaphore->gpu_addr; in cik_sdma_semaphore_ring_emit()
651 u64 gpu_addr; in cik_sdma_ring_test() local
658 gpu_addr = rdev->wb.gpu_addr + index; in cik_sdma_ring_test()
669 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test()
670 radeon_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test()
708 u64 gpu_addr; in cik_sdma_ib_test() local
715 gpu_addr = rdev->wb.gpu_addr + index; in cik_sdma_ib_test()
727 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ib_test()
[all …]
A Duvd_v4_2.c47 addr = (rdev->uvd.gpu_addr + 0x200) >> 3; in uvd_v4_2_resume()
49 addr = rdev->uvd.gpu_addr >> 3; in uvd_v4_2_resume()
67 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v4_2_resume()
71 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v4_2_resume()
A Duvd_v2_2.c43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v2_2_fence_emit()
77 uint64_t addr = semaphore->gpu_addr; in uvd_v2_2_semaphore_emit()
113 addr = rdev->uvd.gpu_addr >> 3; in uvd_v2_2_resume()
130 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v2_2_resume()
134 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v2_2_resume()
A Duvd_v1_0.c85 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v1_0_fence_emit()
121 addr = (rdev->uvd.gpu_addr >> 3) + 16; in uvd_v1_0_resume()
138 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v1_0_resume()
142 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v1_0_resume()
364 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | in uvd_v1_0_start()
374 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr); in uvd_v1_0_start()
487 radeon_ring_write(ring, ib->gpu_addr); in uvd_v1_0_ib_execute()
A Dradeon_semaphore.c51 (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo); in radeon_semaphore_create()
69 ring->last_semaphore_signal_addr = semaphore->gpu_addr; in radeon_semaphore_emit_signal()
86 ring->last_semaphore_wait_addr = semaphore->gpu_addr; in radeon_semaphore_emit_wait()
/drivers/gpu/drm/amd/amdgpu/
A Dvce_v4_0.c157 uint64_t addr = table->gpu_addr; in vce_v4_0_mmsch_start()
235 lower_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start()
237 upper_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start()
263 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
266 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
273 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
276 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
279 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
282 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
658 (adev->vce.gpu_addr >> 8)); in vce_v4_0_mc_resume()
[all …]
A Damdgpu_isp.c180 u64 gpu_addr; in isp_user_buffer_alloc() local
204 AMDGPU_GEM_DOMAIN_GTT, &bo, &gpu_addr); in isp_user_buffer_alloc()
211 *buf_addr = gpu_addr; in isp_user_buffer_alloc()
251 void **buf_obj, u64 *gpu_addr, void **cpu_addr) in isp_kernel_buffer_alloc() argument
266 if (WARN_ON(!gpu_addr)) in isp_kernel_buffer_alloc()
288 gpu_addr, in isp_kernel_buffer_alloc()
311 void isp_kernel_buffer_free(void **buf_obj, u64 *gpu_addr, void **cpu_addr) in isp_kernel_buffer_free() argument
315 amdgpu_bo_free_kernel(bo, gpu_addr, cpu_addr); in isp_kernel_buffer_free()
A Dvcn_v2_0.c409 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
974 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v2_0_start_dpg_mode()
978 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
980 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
1145 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1147 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1897 uint64_t addr = table->gpu_addr; in vcn_v2_0_start_mmsch()
2059 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov()
2062 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov()
2073 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov()
[all …]
A Damdgpu_ih.c70 ih->gpu_addr = dma_addr; in amdgpu_ih_ring_init()
90 &ih->ring_obj, &ih->gpu_addr, in amdgpu_ih_ring_init()
98 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; in amdgpu_ih_ring_init()
100 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; in amdgpu_ih_ring_init()
129 (void *)ih->ring, ih->gpu_addr); in amdgpu_ih_ring_fini()
132 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, in amdgpu_ih_ring_fini()
134 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
135 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
A Dvcn_v5_0_1.c374 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v5_0_1_mc_resume()
376 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v5_0_1_mc_resume()
385 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v5_0_1_mc_resume()
387 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v5_0_1_mc_resume()
401 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v5_0_1_mc_resume()
403 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v5_0_1_mc_resume()
778 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v5_0_1_start_sriov()
781 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v5_0_1_start_sriov()
792 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; in vcn_v5_0_1_start_sriov()
822 rb_enc_addr = ring_enc->gpu_addr; in vcn_v5_0_1_start_sriov()
[all …]
A Dmes_userqueue.c95 queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset_no_check(wptr_obj->obj); in mes_userq_create_wptr_mapping()
133 queue_input.process_context_addr = ctx->gpu_addr; in mes_userq_map()
134 queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ; in mes_userq_map()
140 queue_input.mqd_addr = queue->mqd.gpu_addr; in mes_userq_map()
145 queue_input.wptr_mc_addr = queue->wptr_obj.gpu_addr; in mes_userq_map()
169 queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ; in mes_userq_unmap()
236 userq_props->mqd_gpu_addr = queue->mqd.gpu_addr; in mes_userq_mqd_create()
239 userq_props->fence_address = queue->fence_drv->gpu_addr; in mes_userq_mqd_create()
A Dvcn_v2_5.c1152 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v2_5_start_dpg_mode()
1156 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
1158 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
1334 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1336 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1376 uint64_t addr = table->gpu_addr; in vcn_v2_5_mmsch_start()
1476 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_sriov_start()
1526 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
1529 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
1539 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
[all …]
A Dsi_dma.c90 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib()
174 WREG32(mmDMA_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in si_dma_start()
215 u64 gpu_addr; in si_dma_ring_test_ring() local
221 gpu_addr = adev->wb.gpu_addr + (index * 4); in si_dma_ring_test_ring()
230 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in si_dma_ring_test_ring()
231 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in si_dma_ring_test_ring()
266 u64 gpu_addr; in si_dma_ring_test_ib() local
273 gpu_addr = adev->wb.gpu_addr + (index * 4); in si_dma_ring_test_ib()
283 ib.ptr[1] = lower_32_bits(gpu_addr); in si_dma_ring_test_ib()
284 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in si_dma_ring_test_ib()
[all …]
A Damdgpu_seq64.c174 u64 *gpu_addr, u64 **cpu_addr) in amdgpu_seq64_alloc() argument
186 if (gpu_addr) in amdgpu_seq64_alloc()
187 *gpu_addr = bit_pos * sizeof(u64) + adev->seq64.gpu_addr; in amdgpu_seq64_alloc()
249 &adev->seq64.sbo, &adev->seq64.gpu_addr, in amdgpu_seq64_init()
A Damdgpu_seq64.h35 u64 gpu_addr; member
42 int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *va, u64 *gpu_addr, u64 **cpu_addr);
43 void amdgpu_seq64_free(struct amdgpu_device *adev, u64 gpu_addr);
A Duvd_v7_0.c694 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume()
696 upper_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume()
734 uint64_t addr = table->gpu_addr; in uvd_v7_0_mmsch_start()
836 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_sriov_start()
838 upper_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_sriov_start()
1097 (upper_32_bits(ring->gpu_addr) >> 2)); in uvd_v7_0_start()
1101 lower_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
1103 upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
1333 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v7_0_ring_emit_ib()
1336 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in uvd_v7_0_ring_emit_ib()
[all …]
A Dvcn_v1_0.c364 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
366 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
976 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v1_0_start_spg_mode()
980 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
982 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
1140 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v1_0_start_dpg_mode()
1144 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_dpg_mode()
1146 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_dpg_mode()
1394 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
1396 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
[all …]
A Dvcn_v3_0.c547 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v3_0_mc_resume()
1161 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v3_0_start_dpg_mode()
1165 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start_dpg_mode()
1167 upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start_dpg_mode()
1346 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1348 upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1455 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v3_0_start_sriov()
1458 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v3_0_start_sriov()
1501 rb_addr = ring->gpu_addr; in vcn_v3_0_start_sriov()
1515 rb_addr = ring->gpu_addr; in vcn_v3_0_start_sriov()
[all …]
A Dvcn_v4_0.c479 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_mc_resume()
481 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_mc_resume()
489 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_mc_resume()
491 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_mc_resume()
1412 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_start_sriov()
1415 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_start_sriov()
1426 cache_addr = adev->vcn.inst[i].gpu_addr + offset; in vcn_v4_0_start_sriov()
1440 cache_addr = adev->vcn.inst[i].gpu_addr + offset + in vcn_v4_0_start_sriov()
1460 rb_enc_addr = ring_enc->gpu_addr; in vcn_v4_0_start_sriov()
1489 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); in vcn_v4_0_start_sriov()
[all …]
A Dvce_v3_0.c283 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); in vce_v3_0_start()
284 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
290 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); in vce_v3_0_start()
291 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
297 WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr); in vce_v3_0_start()
298 WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
566 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
570 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
868 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
869 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
[all …]
A Damdgpu_sa.c54 &sa_manager->bo, &sa_manager->gpu_addr, in amdgpu_sa_bo_manager_init()
76 amdgpu_bo_free_kernel(&sa_manager->bo, &sa_manager->gpu_addr, &sa_manager->cpu_ptr); in amdgpu_sa_bo_manager_fini()
113 drm_suballoc_dump_debug_info(&sa_manager->base, &p, sa_manager->gpu_addr); in amdgpu_sa_bo_dump_debug_info()
A Dvcn_v4_0_3.c480 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); in vcn_v4_0_3_mc_resume()
483 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); in vcn_v4_0_3_mc_resume()
954 lower_32_bits(ring->gpu_addr)); in vcn_v4_0_3_start_dpg_mode()
956 upper_32_bits(ring->gpu_addr)); in vcn_v4_0_3_start_dpg_mode()
1056 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_3_start_sriov()
1059 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_3_start_sriov()
1070 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; in vcn_v4_0_3_start_sriov()
1100 rb_enc_addr = ring_enc->gpu_addr; in vcn_v4_0_3_start_sriov()
1129 ctx_addr = table->gpu_addr; in vcn_v4_0_3_start_sriov()
1321 lower_32_bits(ring->gpu_addr)); in vcn_v4_0_3_start()
[all …]
A Dsdma_v2_4.c260 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
261 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
538 u64 gpu_addr; in sdma_v2_4_ring_test_ring() local
544 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v2_4_ring_test_ring()
554 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
555 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
591 u64 gpu_addr; in sdma_v2_4_ring_test_ib() local
598 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v2_4_ring_test_ib()
609 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
610 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
[all …]
/drivers/gpu/drm/amd/amdkfd/
A Dkfd_mqd_manager.c58 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr; in allocate_hiq_mqd()
84 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; in allocate_sdma_mqd()
285 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; in kfd_get_hiq_xcc_mqd()

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