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Searched refs:gpu_write (Results 1 – 25 of 28) sorted by relevance

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/drivers/gpu/drm/msm/adreno/
A Da3xx_gpu.c221 gpu_write(gpu, REG_A3XX_RBBM_SP_HYST_CNT, 0x10); in a3xx_hw_init()
262 gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR, in a3xx_hw_init()
267 gpu_write(gpu, REG_A3XX_RBBM_PERFCTR_CTL, 0x01); in a3xx_hw_init()
285 gpu_write(gpu, REG_AXXX_CP_RB_CNTL, in a3xx_hw_init()
326 gpu_write(gpu, REG_AXXX_CP_DEBUG, in a3xx_hw_init()
329 gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0); in a3xx_hw_init()
338 gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0); in a3xx_hw_init()
347 gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, in a3xx_hw_init()
361 gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0); in a3xx_hw_init()
381 gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1); in a3xx_recover()
[all …]
A Da4xx_gpu.c108 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_RB(i), in a4xx_enable_hwcg()
111 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_RB(i), in a4xx_enable_hwcg()
149 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0); in a4xx_enable_hwcg()
152 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2, 0); in a4xx_enable_hwcg()
239 gpu_write(gpu, REG_A4XX_RB_GMEM_BASE_ADDR, in a4xx_hw_init()
257 gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) | in a4xx_hw_init()
321 gpu_write(gpu, REG_A4XX_CP_RB_CNTL, in a4xx_hw_init()
331 gpu_write(gpu, REG_A4XX_CP_ME_RAM_WADDR, 0); in a4xx_hw_init()
340 gpu_write(gpu, REG_A4XX_CP_PFP_UCODE_ADDR, 0); in a4xx_hw_init()
345 gpu_write(gpu, REG_A4XX_CP_ME_CNTL, 0); in a4xx_hw_init()
[all …]
A Da5xx_power.c130 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a530_lm_setup()
151 gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x201FF1); in a530_lm_setup()
153 gpu_write(gpu, AGC_MSG_STATE, 1); in a530_lm_setup()
157 gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448); in a530_lm_setup()
158 gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1); in a530_lm_setup()
193 gpu_write(gpu, AGC_MSG_STATE, 0x80000001); in a540_lm_setup()
196 gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448); in a540_lm_setup()
197 gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1); in a540_lm_setup()
204 gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE, in a540_lm_setup()
286 gpu_write(gpu, REG_A5XX_GDPM_INT_MASK, 0x0); in a5xx_lm_enable()
[all …]
A Da5xx_gpu.c63 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
465 gpu_write(gpu, regs[i].offset, in a5xx_set_hwcg()
789 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
793 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
796 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
863 gpu_write(gpu, REG_A5XX_CP_PROTECT(6), in a5xx_hw_init()
866 gpu_write(gpu, REG_A5XX_CP_PROTECT(7), in a5xx_hw_init()
887 gpu_write(gpu, REG_A5XX_CP_PROTECT(17), in a5xx_hw_init()
942 gpu_write(gpu, REG_A5XX_CP_RB_CNTL, in a5xx_hw_init()
957 gpu_write(gpu, REG_A5XX_CP_PFP_ME_CNTL, 0); in a5xx_hw_init()
[all …]
A Da2xx_gpu.c161 gpu_write(gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_hw_init()
165 gpu_write(gpu, REG_A2XX_MH_ARBITER_CONFIG, in a2xx_hw_init()
191 gpu_write(gpu, REG_A2XX_RBBM_INT_CNTL, in a2xx_hw_init()
193 gpu_write(gpu, REG_AXXX_CP_INT_CNTL, in a2xx_hw_init()
201 gpu_write(gpu, REG_A2XX_SQ_INT_CNTL, 0); in a2xx_hw_init()
202 gpu_write(gpu, REG_A2XX_MH_INTERRUPT_MASK, in a2xx_hw_init()
210 gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i); in a2xx_hw_init()
216 gpu_write(gpu, REG_AXXX_CP_RB_CNTL, in a2xx_hw_init()
243 gpu_write(gpu, REG_AXXX_CP_DEBUG, in a2xx_hw_init()
245 gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0); in a2xx_hw_init()
[all …]
A Da6xx_gpu.c89 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); in a6xx_flush()
593 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, in a6xx_set_cp_protect()
703 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, in a6xx_set_ubwc_config()
715 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, in a6xx_set_ubwc_config()
725 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, in a6xx_set_ubwc_config()
1082 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); in hw_init()
1088 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); in hw_init()
1292 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, in hw_init()
1299 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, in hw_init()
1315 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, in hw_init()
[all …]
A Da6xx_gpu_state.c163 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
168 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
227 gpu_write(gpu, ctrl0, reg); in vbif_debugbus_read()
230 gpu_write(gpu, ctrl1, i); in vbif_debugbus_read()
264 gpu_write(gpu, REG_A6XX_VBIF_CLKON, in a6xx_get_vbif_debugbus_block()
268 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS1_CTRL0, 0); in a6xx_get_vbif_debugbus_block()
297 gpu_write(gpu, REG_A6XX_VBIF_CLKON, clk); in a6xx_get_vbif_debugbus_block()
439 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLT, in a6xx_get_debugbus()
442 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLM, in a6xx_get_debugbus()
1463 gpu_write(gpu, indexed->addr, 0); in a6xx_get_indexed_regs()
[all …]
A Da5xx_debugfs.c21 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i); in pfp_print()
34 gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i); in me_print()
45 gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0); in meq_print()
58 gpu_write(gpu, REG_A5XX_CP_ROQ_DBG_ADDR, 0); in roq_print()
A Da2xx_gpummu.c56 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_map()
71 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_unmap()
A Da6xx_preempt.c54 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); in update_wptr()
213 gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0x1); in a6xx_preempt_hw_init()
331 gpu_write(gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL, cntl); in a6xx_preempt_trigger()
A Da5xx_preempt.c52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
168 gpu_write(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL, 1); in a5xx_preempt_trigger()
/drivers/gpu/drm/panfrost/
A Dpanfrost_perfcnt.c57 gpu_write(pfdev, GPU_INT_CLEAR, in panfrost_perfcnt_dump_locked()
121 gpu_write(pfdev, GPU_INT_CLEAR, in panfrost_perfcnt_enable_locked()
155 gpu_write(pfdev, GPU_PRFCNT_TILER_EN, 0); in panfrost_perfcnt_enable_locked()
159 gpu_write(pfdev, GPU_PERFCNT_CFG, cfg); in panfrost_perfcnt_enable_locked()
192 gpu_write(pfdev, GPU_PRFCNT_JM_EN, 0x0); in panfrost_perfcnt_disable_locked()
195 gpu_write(pfdev, GPU_PRFCNT_TILER_EN, 0); in panfrost_perfcnt_disable_locked()
196 gpu_write(pfdev, GPU_PERFCNT_CFG, in panfrost_perfcnt_disable_locked()
328 gpu_write(pfdev, GPU_PERFCNT_CFG, in panfrost_perfcnt_init()
330 gpu_write(pfdev, GPU_PRFCNT_JM_EN, 0); in panfrost_perfcnt_init()
345 gpu_write(pfdev, GPU_PERFCNT_CFG, in panfrost_perfcnt_fini()
[all …]
A Dpanfrost_gpu.c46 gpu_write(pfdev, GPU_INT_MASK, 0); in panfrost_gpu_irq_handler()
55 gpu_write(pfdev, GPU_INT_CLEAR, state); in panfrost_gpu_irq_handler()
65 gpu_write(pfdev, GPU_INT_MASK, 0); in panfrost_gpu_soft_reset()
70 gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); in panfrost_gpu_soft_reset()
77 gpu_write(pfdev, GPU_CMD, GPU_CMD_HARD_RESET); in panfrost_gpu_soft_reset()
89 gpu_write(pfdev, GPU_INT_MASK, in panfrost_gpu_soft_reset()
143 gpu_write(pfdev, GPU_SHADER_CONFIG, quirks); in panfrost_gpu_init_quirks()
152 gpu_write(pfdev, GPU_TILER_CONFIG, quirks); in panfrost_gpu_init_quirks()
168 gpu_write(pfdev, GPU_JM_CONFIG, quirks); in panfrost_gpu_init_quirks()
437 gpu_write(pfdev, SHADER_PWRON_LO, in panfrost_gpu_power_on()
[all …]
A Dpanfrost_regs.h373 #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg) macro
/drivers/gpu/drm/etnaviv/
A Detnaviv_iommu.c100 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base); in etnaviv_iommuv1_restore()
101 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base); in etnaviv_iommuv1_restore()
102 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base); in etnaviv_iommuv1_restore()
103 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base); in etnaviv_iommuv1_restore()
104 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base); in etnaviv_iommuv1_restore()
109 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
110 gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
111 gpu_write(gpu, VIVS_MC_MMU_PE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
112 gpu_write(gpu, VIVS_MC_MMU_PEZ_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
113 gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
A Detnaviv_iommu_v2.c186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
203 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW, in etnaviv_iommuv2_restore_sec()
205 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH, in etnaviv_iommuv2_restore_sec()
207 gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
209 gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
211 gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
213 gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG, in etnaviv_iommuv2_restore_sec()
228 gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
A Detnaviv_gpu.c501 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
503 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
560 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
563 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
576 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
580 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
696 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
701 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
786 gpu_write(gpu, VIVS_HI_AXI_CONFIG, in etnaviv_gpu_hw_init()
803 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); in etnaviv_gpu_hw_init()
[all …]
A Detnaviv_perfmon.c44 gpu_write(gpu, domain->profile_config, signal->data); in perf_reg_read()
54 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_select()
A Detnaviv_sched.c59 gpu_write(gpu, VIVS_MC_PROFILE_CONFIG0, in etnaviv_sched_timedout_job()
A Detnaviv_gpu.h170 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() function
/drivers/gpu/drm/panthor/
A Dpanthor_device.h399 gpu_write(ptdev, __reg_prefix ## _INT_MASK, 0); \
420 gpu_write(ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \
428 gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, 0); \
437 gpu_write(pirq->ptdev, __reg_prefix ## _INT_CLEAR, mask); \
438 gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, mask); \
458 static inline void gpu_write(struct panthor_device *ptdev, u32 reg, u32 data) in gpu_write() function
475 gpu_write(ptdev, reg, lower_32_bits(data)); in gpu_write64()
476 gpu_write(ptdev, reg + 4, upper_32_bits(data)); in gpu_write64()
A Dpanthor_gpu.c82 gpu_write(ptdev, GPU_COHERENCY_PROTOCOL, in panthor_gpu_coherency_set()
148 gpu_write(ptdev, GPU_INT_CLEAR, status); in panthor_gpu_irq_handler()
360 gpu_write(ptdev, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other)); in panthor_gpu_flush_caches()
399 gpu_write(ptdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); in panthor_gpu_soft_reset()
400 gpu_write(ptdev, GPU_CMD, GPU_SOFT_RESET); in panthor_gpu_soft_reset()
A Dpanthor_fw.c1004 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_init_global_iface()
1013 gpu_write(ptdev, JOB_INT_CLEAR, status); in panthor_job_irq_handler()
1034 gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_AUTO); in panthor_fw_start()
1065 gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_DISABLE); in panthor_fw_stop()
1091 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_pre_reset()
1309 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_ring_csg_doorbells()
1324 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_ping_work()
A Dpanthor_mmu.c532 gpu_write(ptdev, AS_COMMAND(as_nr), cmd); in write_cmd()
771 gpu_write(ptdev, MMU_INT_CLEAR, panthor_mmu_as_fault_mask(ptdev, as)); in panthor_vm_active()
774 gpu_write(ptdev, MMU_INT_MASK, ~ptdev->mmu->as.faulty_mask); in panthor_vm_active()
1695 gpu_write(ptdev, MMU_INT_CLEAR, mask); in panthor_mmu_irq_handler()
/drivers/gpu/drm/msm/
A Dmsm_gpu.h614 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) in gpu_write() function

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