| /drivers/gpu/drm/amd/display/dc/hubbub/dcn30/ |
| A D | dcn30_hubbub.c | 345 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub3_get_dcc_compression_cap()
346 output->grph.rgb.max_compressed_blk_size = 256; in hubbub3_get_dcc_compression_cap()
347 output->grph.rgb.independent_64b_blks = false; in hubbub3_get_dcc_compression_cap()
353 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub3_get_dcc_compression_cap()
354 output->grph.rgb.max_compressed_blk_size = 128; in hubbub3_get_dcc_compression_cap()
355 output->grph.rgb.independent_64b_blks = false; in hubbub3_get_dcc_compression_cap()
362 output->grph.rgb.max_compressed_blk_size = 64; in hubbub3_get_dcc_compression_cap()
363 output->grph.rgb.independent_64b_blks = true; in hubbub3_get_dcc_compression_cap()
364 output->grph.rgb.dcc_controls.dcc_256_64_64 = 1; in hubbub3_get_dcc_compression_cap()
368 output->grph.rgb.max_compressed_blk_size = 128; in hubbub3_get_dcc_compression_cap()
[all …]
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| /drivers/gpu/drm/amd/display/dc/hubbub/dcn31/ |
| A D | dcn31_hubbub.c | 872 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub31_get_dcc_compression_cap()
873 output->grph.rgb.max_compressed_blk_size = 256; in hubbub31_get_dcc_compression_cap()
874 output->grph.rgb.independent_64b_blks = false; in hubbub31_get_dcc_compression_cap()
879 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub31_get_dcc_compression_cap()
880 output->grph.rgb.max_compressed_blk_size = 128; in hubbub31_get_dcc_compression_cap()
881 output->grph.rgb.independent_64b_blks = false; in hubbub31_get_dcc_compression_cap()
888 output->grph.rgb.max_compressed_blk_size = 64; in hubbub31_get_dcc_compression_cap()
889 output->grph.rgb.independent_64b_blks = true; in hubbub31_get_dcc_compression_cap()
890 output->grph.rgb.dcc_controls.dcc_256_64_64 = 1; in hubbub31_get_dcc_compression_cap()
895 output->grph.rgb.max_compressed_blk_size = 128; in hubbub31_get_dcc_compression_cap()
[all …]
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| /drivers/gpu/drm/amd/display/dc/hubbub/dcn20/ |
| A D | dcn20_hubbub.c | 285 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
286 output->grph.rgb.max_compressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
287 output->grph.rgb.independent_64b_blks = false; in hubbub2_get_dcc_compression_cap()
290 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub2_get_dcc_compression_cap()
291 output->grph.rgb.max_compressed_blk_size = 128; in hubbub2_get_dcc_compression_cap()
292 output->grph.rgb.independent_64b_blks = false; in hubbub2_get_dcc_compression_cap()
295 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
296 output->grph.rgb.max_compressed_blk_size = 64; in hubbub2_get_dcc_compression_cap()
297 output->grph.rgb.independent_64b_blks = true; in hubbub2_get_dcc_compression_cap()
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| /drivers/gpu/drm/amd/display/dmub/src/ |
| A D | dmub_dcn32.c | 525 REG_WRITE(DMCUB_SCRATCH9, addr->grph.addr.low_part); in dmub_dcn32_save_surf_addr()
526 REG_WRITE(DMCUB_SCRATCH11, addr->grph.meta_addr.low_part); in dmub_dcn32_save_surf_addr()
528 REG_WRITE(DMCUB_SCRATCH12, addr->grph.addr.low_part); in dmub_dcn32_save_surf_addr()
529 REG_WRITE(DMCUB_SCRATCH13, addr->grph.meta_addr.low_part); in dmub_dcn32_save_surf_addr()
535 REG_WRITE(DMCUB_SCRATCH18, addr->grph.addr.low_part); in dmub_dcn32_save_surf_addr()
536 REG_WRITE(DMCUB_SCRATCH19, addr->grph.meta_addr.low_part); in dmub_dcn32_save_surf_addr()
538 REG_WRITE(DMCUB_SCRATCH20, addr->grph.addr.low_part); in dmub_dcn32_save_surf_addr()
539 REG_WRITE(DMCUB_SCRATCH22, addr->grph.meta_addr.low_part); in dmub_dcn32_save_surf_addr()
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| /drivers/gpu/drm/amd/display/dc/hubp/dcn30/ |
| A D | dcn30_hubp.c | 108 if (address->grph.addr.quad_part == 0) in hubp3_program_surface_flip_and_addr()
115 if (address->grph.meta_addr.quad_part != 0) { in hubp3_program_surface_flip_and_addr()
118 address->grph.meta_addr.high_part); in hubp3_program_surface_flip_and_addr()
122 address->grph.meta_addr.low_part); in hubp3_program_surface_flip_and_addr()
127 address->grph.addr.high_part); in hubp3_program_surface_flip_and_addr()
131 address->grph.addr.low_part); in hubp3_program_surface_flip_and_addr()
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| /drivers/gpu/drm/amd/display/dc/hubbub/dcn10/ |
| A D | dcn10_hubbub.c | 889 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
890 output->grph.rgb.max_compressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
891 output->grph.rgb.independent_64b_blks = false; in hubbub1_get_dcc_compression_cap()
894 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub1_get_dcc_compression_cap()
895 output->grph.rgb.max_compressed_blk_size = 128; in hubbub1_get_dcc_compression_cap()
896 output->grph.rgb.independent_64b_blks = false; in hubbub1_get_dcc_compression_cap()
899 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
900 output->grph.rgb.max_compressed_blk_size = 64; in hubbub1_get_dcc_compression_cap()
901 output->grph.rgb.independent_64b_blks = true; in hubbub1_get_dcc_compression_cap()
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| /drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| A D | dcn10_hubp.c | 388 if (address->grph.addr.quad_part == 0) in hubp1_program_surface_flip_and_addr()
395 if (address->grph.meta_addr.quad_part != 0) { in hubp1_program_surface_flip_and_addr()
398 address->grph.meta_addr.high_part); in hubp1_program_surface_flip_and_addr()
402 address->grph.meta_addr.low_part); in hubp1_program_surface_flip_and_addr()
407 address->grph.addr.high_part); in hubp1_program_surface_flip_and_addr()
411 address->grph.addr.low_part); in hubp1_program_surface_flip_and_addr()
764 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); in hubp1_is_flip_pending()
767 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); in hubp1_is_flip_pending()
773 earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) in hubp1_is_flip_pending()
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| /drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| A D | dcn20_hubp.c | 756 if (address->grph.addr.quad_part == 0) in hubp2_program_surface_flip_and_addr()
763 if (address->grph.meta_addr.quad_part != 0) { in hubp2_program_surface_flip_and_addr()
766 address->grph.meta_addr.high_part); in hubp2_program_surface_flip_and_addr()
770 address->grph.meta_addr.low_part); in hubp2_program_surface_flip_and_addr()
775 address->grph.addr.high_part); in hubp2_program_surface_flip_and_addr()
779 address->grph.addr.low_part); in hubp2_program_surface_flip_and_addr()
936 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); in hubp2_is_flip_pending()
939 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); in hubp2_is_flip_pending()
945 earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) in hubp2_is_flip_pending()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_debug.c | 72 update->flip_addr->address.grph.addr.quad_part, in update_surface_trace()
73 update->flip_addr->address.grph.meta_addr.quad_part, in update_surface_trace()
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| /drivers/gpu/drm/amd/display/dc/hubp/dcn21/ |
| A D | dcn21_hubp.c | 709 if (address->grph.addr.quad_part == 0) { in hubp21_program_surface_flip_and_addr()
714 if (address->grph.meta_addr.quad_part != 0) { in hubp21_program_surface_flip_and_addr()
716 address->grph.meta_addr.low_part; in hubp21_program_surface_flip_and_addr()
718 address->grph.meta_addr.high_part; in hubp21_program_surface_flip_and_addr()
722 address->grph.addr.low_part; in hubp21_program_surface_flip_and_addr()
724 address->grph.addr.high_part; in hubp21_program_surface_flip_and_addr()
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| /drivers/gpu/drm/amd/display/dc/hubbub/dcn401/ |
| A D | dcn401_hubbub.c | 977 output->grph.rgb.dcc_controls.dcc_256_256 = 1; in hubbub401_get_dcc_compression_cap()
978 output->grph.rgb.dcc_controls.dcc_256_128 = 1; in hubbub401_get_dcc_compression_cap()
979 output->grph.rgb.dcc_controls.dcc_256_64 = 1; in hubbub401_get_dcc_compression_cap()
982 output->grph.rgb.dcc_controls.dcc_256_128 = 1; in hubbub401_get_dcc_compression_cap()
983 output->grph.rgb.dcc_controls.dcc_256_64 = 1; in hubbub401_get_dcc_compression_cap()
986 output->grph.rgb.dcc_controls.dcc_256_64 = 1; in hubbub401_get_dcc_compression_cap()
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| /drivers/gpu/drm/amd/display/dc/hwss/dce60/ |
| A D | dce60_hwseq.c | 351 pipe_ctx->plane_state->address.grph.addr.high_part, in dce60_program_front_end_for_pipe()
352 pipe_ctx->plane_state->address.grph.addr.low_part, in dce60_program_front_end_for_pipe()
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| /drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| A D | dcn401_hubp.c | 405 if (address->grph.addr.quad_part == 0) in hubp401_program_surface_flip_and_addr()
413 address->grph.addr.high_part); in hubp401_program_surface_flip_and_addr()
417 address->grph.addr.low_part); in hubp401_program_surface_flip_and_addr()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_plane.c | 304 output.grph.rgb.independent_64b_blks != 0) in amdgpu_dm_plane_validate_dcc()
350 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
351 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
870 address->grph.addr.low_part = lower_32_bits(addr); in amdgpu_dm_plane_fill_plane_buffer_attributes()
871 address->grph.addr.high_part = upper_32_bits(addr); in amdgpu_dm_plane_fill_plane_buffer_attributes()
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| A D | amdgpu_dm.c | 9504 bundle->flip_addrs[planes_count].address.grph.addr.high_part, in amdgpu_dm_commit_planes()
9505 bundle->flip_addrs[planes_count].address.grph.addr.low_part); in amdgpu_dm_commit_planes()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| A D | dcn201_hwseq.c | 112 gpu_addr_to_uma(hwseq, &addr->grph.addr); in plane_address_in_gpu_space_to_uma()
113 gpu_addr_to_uma(hwseq, &addr->grph.meta_addr); in plane_address_in_gpu_space_to_uma()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_mem_input.c | 871 if (address->grph.addr.quad_part == 0) in dce_mi_program_surface_flip_and_addr()
873 program_pri_addr(dce_mi, address->grph.addr); in dce_mi_program_surface_flip_and_addr()
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc_dmub_srv.c | 1886 if (address->grph.addr.quad_part == 0) { in dc_dmub_srv_fams2_passthrough_flip()
1892 address->grph.meta_addr.low_part; in dc_dmub_srv_fams2_passthrough_flip()
1894 (uint16_t)address->grph.meta_addr.high_part; in dc_dmub_srv_fams2_passthrough_flip()
1896 address->grph.addr.low_part; in dc_dmub_srv_fams2_passthrough_flip()
1898 (uint16_t)address->grph.addr.high_part; in dc_dmub_srv_fams2_passthrough_flip()
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| A D | dc_hw_types.h | 78 } grph; member
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| A D | dc.h | 402 } grph; member
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| A D | dcn30_hwseq.c | 951 plane->address.grph.cursor_cache_addr.quad_part; in dcn30_apply_idle_power_optimizations()
1059 (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047; in dcn30_apply_idle_power_optimizations()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_mem_input_v.c | 136 addr->grph.addr); in program_addr()
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| /drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| A D | dce110_hwseq.c | 2989 pipe_ctx->plane_state->address.grph.addr.high_part, in dce110_program_front_end_for_pipe()
2990 pipe_ctx->plane_state->address.grph.addr.low_part, in dce110_program_front_end_for_pipe()
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