| /drivers/gpu/drm/amd/display/dc/dpp/dcn32/ |
| A D | dcn32_dpp.c | 67 if (scl_data->viewport.width == scl_data->h_active && in dscl32_calc_lb_num_partitions()
81 if (scl_data->viewport.width == scl_data->h_active && in dscl32_calc_lb_num_partitions()
200 if (scl_data->viewport.width == scl_data->h_active && in dscl32_spl_calc_lb_num_partitions()
214 if (scl_data->viewport.width == scl_data->h_active && in dscl32_spl_calc_lb_num_partitions()
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| /drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| A D | dcn401_dpp.c | 316 if (scl_data->viewport.width == scl_data->h_active && in dscl401_calc_lb_num_partitions()
330 if (scl_data->viewport.width == scl_data->h_active && in dscl401_calc_lb_num_partitions()
391 if (scl_data->viewport.width == scl_data->h_active && in dscl401_spl_calc_lb_num_partitions()
405 if (scl_data->viewport.width == scl_data->h_active && in dscl401_spl_calc_lb_num_partitions()
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| /drivers/staging/media/max96712/ |
| A D | max96712.c | 160 const u32 h_active = 1920; in max96712_pattern_enable() local
164 const u32 h_tot = h_active + h_fp + h_sw + h_bp; in max96712_pattern_enable()
188 max96712_write_bulk_value(priv, 0x1060, h_active + h_fp + h_bp, 2); in max96712_pattern_enable()
192 max96712_write_bulk_value(priv, 0x1067, h_active, 2); in max96712_pattern_enable()
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| /drivers/gpu/drm/amd/display/dc/optc/dcn401/ |
| A D | dcn401_optc.c | 57 static uint32_t decide_odm_mem_bit_map(int *opp_id, int opp_cnt, int h_active) in decide_odm_mem_bit_map() argument
62 int total_required = ((h_active + 4095) / 4096) * 2; in decide_odm_mem_bit_map()
108 uint32_t h_active = segment_width * (opp_cnt - 1) + last_segment_width; in optc401_set_odm_combine() local
110 opp_id, opp_cnt, h_active); in optc401_set_odm_combine()
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_audio.c | 457 unsigned int h_active, h_total, hblank_delta, pixel_clk; in calc_hblank_early_prog() local
462 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; in calc_hblank_early_prog()
474 h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk); in calc_hblank_early_prog()
479 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; in calc_hblank_early_prog()
490 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), in calc_hblank_early_prog()
496 return h_active - hblank_rise + hblank_delta; in calc_hblank_early_prog()
501 unsigned int h_active, h_total, pixel_clk; in calc_samples_room() local
504 h_active = crtc_state->hw.adjusted_mode.hdisplay; in calc_samples_room()
510 return ((h_total - h_active) * link_clk - 12 * pixel_clk) / in calc_samples_room()
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| A D | intel_sdvo_regs.h | 79 u8 h_active; /* lower 8 bits (pixels) */ member
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| /drivers/gpu/drm/amd/display/dc/optc/dcn314/ |
| A D | dcn314_optc.c | 55 int h_active = segment_width * opp_cnt; in optc314_set_odm_combine() local
57 int odm_mem_count = (h_active + 2047) / 2048; in optc314_set_odm_combine()
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| /drivers/gpu/drm/amd/display/dc/optc/dcn32/ |
| A D | dcn32_optc.c | 50 int h_active = segment_width * opp_cnt; in optc32_set_odm_combine() local
52 int odm_mem_count = (h_active + 2047) / 2048; in optc32_set_odm_combine()
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| /drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| A D | dcn201_dpp.c | 196 if (scl_data->viewport.width != scl_data->h_active && in dpp201_get_optimal_number_of_taps()
202 if (scl_data->viewport.width > scl_data->h_active && in dpp201_get_optimal_number_of_taps()
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| /drivers/gpu/drm/amd/display/include/ |
| A D | audio_types.h | 48 uint32_t h_active; member
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| /drivers/video/fbdev/via/ |
| A D | chip.h | 128 int h_active; member
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| A D | dvi.c | 331 if ((viaparinfo->tmds_setting_info->h_active == 1600) && in dvi_patch_skew_dvp0()
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc_spl_translate.c | 197 spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active; in translate_SPL_in_params_from_pipe_ctx()
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| /drivers/media/i2c/ |
| A D | max96714.c | 151 const u32 h_active = fmt->width; in max96714_apply_patgen_timing() local
163 h_tot = h_active + h_fp + h_sw + h_bp; in max96714_apply_patgen_timing()
178 cci_write(priv->regmap, MAX96714_PATGEN_HS_LOW, h_active + h_fp + h_bp, in max96714_apply_patgen_timing()
183 cci_write(priv->regmap, MAX96714_PATGEN_DE_HIGH, h_active, &ret); in max96714_apply_patgen_timing()
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| A D | max96717.c | 175 const u32 h_active = fmt->width; in max96717_apply_patgen_timing() local
187 h_tot = h_active + h_fp + h_sw + h_bp; in max96717_apply_patgen_timing()
202 cci_write(priv->regmap, MAX96717_VTX_HS_LOW, h_active + h_fp + h_bp, in max96717_apply_patgen_timing()
207 cci_write(priv->regmap, MAX96717_VTX_DE_HIGH, h_active, &ret); in max96717_apply_patgen_timing()
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| /drivers/gpu/drm/amd/display/dc/optc/dcn35/ |
| A D | dcn35_optc.c | 63 int h_active = segment_width * opp_cnt; in optc35_set_odm_combine() local
65 int odm_mem_count = (h_active + 2047) / 2048; in optc35_set_odm_combine()
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| /drivers/gpu/drm/amd/display/dc/sspl/ |
| A D | dc_spl_types.h | 133 int h_active; member
551 int h_active; member
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| A D | dc_spl.c | 244 int h_active = spl_in->basic_out.output_size.width; in calculate_odm_slice_in_timing_active() local
250 odm_slice_width = h_active / odm_slice_count; in calculate_odm_slice_in_timing_active()
261 h_active - odm_slice_width * (odm_slice_count - 1) : in calculate_odm_slice_in_timing_active()
979 if (spl_scratch->scl_data.viewport.width > spl_scratch->scl_data.h_active && in spl_get_optimal_number_of_taps()
1238 dscl_prog_data->mpc_size.width = spl_scratch->scl_data.h_active; in spl_set_dscl_prog_data()
1808 spl_scratch->scl_data.h_active = spl_in->h_active; in spl_calculate_number_of_taps()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | transform.h | 154 int h_active; member
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/ |
| A D | dml2_top_soc15.c | 472 static bool calculate_h_split_for_scaling_transform(int full_vp_width, int h_active, int num_pipes, in calculate_h_split_for_scaling_transform() argument
547 …ath_ceil(plane->composition.scaler_info.plane0.h_ratio * stream->timing.h_active / odm_combine_fac… in dml2_top_mcache_validate_admissability()
553 …ath_ceil(plane->composition.scaler_info.plane1.h_ratio * stream->timing.h_active / odm_combine_fac… in dml2_top_mcache_validate_admissability()
593 stream->timing.h_active, num_dpps, scaling_transform, in dml2_top_mcache_validate_admissability()
604 stream->timing.h_active, num_dpps, scaling_transform, in dml2_top_mcache_validate_admissability()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| A D | dml_top_display_cfg_types.h | 253 unsigned long h_active; member
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| /drivers/gpu/drm/kmb/ |
| A D | kmb_dsi.h | 288 u32 h_active; member
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| /drivers/gpu/drm/gma500/ |
| A D | psb_intel_sdvo_regs.h | 68 u8 h_active; /**< lower 8 bits (pixels) */ member
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_audio.c | 165 h_blank = crtc_info->h_total - crtc_info->h_active; in check_audio_bandwidth_hdmi()
398 uint64_t hblank = crtc_info->h_total - crtc_info->h_active; in calculate_available_hblank_bw_in_symbols()
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| /drivers/video/fbdev/ |
| A D | smscufx.c | 662 u16 h_total, h_active, h_blank_start, h_blank_end, h_sync_start, h_sync_end; in ufx_set_vid_mode() local
686 h_active = var->xres; in ufx_set_vid_mode()
692 temp = ((h_total - 1) << 16) | (h_active - 1); in ufx_set_vid_mode()
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