| /drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_timing_generator.c | 295 uint32_t h_sync_start = dc_crtc_timing->h_addressable + hsync_offset; in dce110_timing_generator_program_timing_generator()
310 bp_params.h_addressable = in dce110_timing_generator_program_timing_generator()
311 patched_crtc_timing.h_addressable; in dce110_timing_generator_program_timing_generator()
610 uint32_t h_sync_start = timing->h_addressable + hsync_offset; in dce110_timing_generator_program_blanking()
669 tmp = tmp + timing->h_addressable + in dce110_timing_generator_program_blanking()
1129 h_sync_start = timing->h_addressable + hsync_offset; in dce110_timing_generator_validate_timing()
1148 h_blank = (timing->h_total - timing->h_addressable - in dce110_timing_generator_validate_timing()
1159 timing->h_addressable - in dce110_timing_generator_validate_timing()
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| A D | dce110_timing_generator_v.c | 251 uint32_t h_sync_start = timing->h_addressable + hsync_offset; in dce110_timing_generator_v_program_blanking()
288 tmp = tmp + timing->h_addressable + in dce110_timing_generator_v_program_blanking()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource_helpers.c | 265 …if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 19… in override_det_for_subvp()
278 …if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 19… in override_det_for_subvp()
595 if (pipe->stream->timing.h_addressable == width && in dcn32_check_native_scaling_for_res()
624 if (pipe->stream->timing.v_addressable == 1080 && pipe->stream->timing.h_addressable == 1920) in disallow_subvp_in_active_plus_blank()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_translation_helper.c | 429 …timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_… in populate_dml21_timing_config_from_stream_state()
443 timing->h_blank_end = hblank_start - stream->timing.h_addressable in populate_dml21_timing_config_from_stream_state()
446 if (hblank_start < stream->timing.h_addressable) in populate_dml21_timing_config_from_stream_state()
718 surface->plane0.width = stream->timing.h_addressable; in populate_dml21_dummy_surface_cfg()
720 surface->plane1.width = stream->timing.h_addressable; in populate_dml21_dummy_surface_cfg()
736 if (stream->timing.h_addressable > 3840) in populate_dml21_dummy_plane_cfg()
739 width = stream->timing.h_addressable; // 4K max in populate_dml21_dummy_plane_cfg()
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| /drivers/gpu/drm/amd/display/dc/link/ |
| A D | link_validation.c | 155 if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable) in dp_active_dongle_validate_timing()
291 timing->h_addressable == (uint32_t) 640 && in dp_validate_mode_timing()
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| A D | link_dpms.c | 835 dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->hblank_borrow + in link_set_dsc_on_stream()
967 …dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h… in link_set_dsc_pps_packet()
1971 bool is_vga_mode = (stream->timing.h_addressable == 640) in enable_link_hdmi()
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| /drivers/gpu/drm/amd/display/dc/optc/dcn201/ |
| A D | dcn201_optc.c | 82 h_blank = (timing->h_total - timing->h_addressable - in optc201_validate_timing()
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| /drivers/gpu/drm/amd/display/dc/bios/ |
| A D | command_table2.c | 618 params.h_size = cpu_to_le16((uint16_t)bp_params->h_addressable); in set_crtc_using_dtd_timing_v3()
622 bp_params->h_addressable)); in set_crtc_using_dtd_timing_v3()
635 bp_params->h_addressable)); in set_crtc_using_dtd_timing_v3()
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| A D | command_table.c | 1836 params.usH_Disp = cpu_to_le16((uint16_t)(bp_params->h_addressable)); in set_crtc_timing_v1()
1909 params.usH_Size = cpu_to_le16((uint16_t)bp_params->h_addressable); in set_crtc_using_dtd_timing_v3()
1912 cpu_to_le16((uint16_t)(bp_params->h_total - bp_params->h_addressable)); in set_crtc_using_dtd_timing_v3()
1922 cpu_to_le16((uint16_t)(bp_params->h_sync_start - bp_params->h_addressable)); in set_crtc_using_dtd_timing_v3()
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| /drivers/gpu/drm/amd/display/include/ |
| A D | bios_parser_types.h | 173 uint32_t h_addressable; member
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| /drivers/gpu/drm/amd/display/dc/hpo/dcn31/ |
| A D | dcn31_hpo_dp_stream_encoder.c | 348 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; in dcn31_hpo_dp_stream_enc_set_stream_attribute()
360 …h_width = hw_crtc_timing.h_border_left + hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_ri… in dcn31_hpo_dp_stream_enc_set_stream_attribute()
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| /drivers/gpu/drm/amd/display/dc/dio/dcn401/ |
| A D | dcn401_dio_stream_encoder.c | 668 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; in enc401_stream_encoder_dp_set_stream_attribute()
700 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, in enc401_stream_encoder_dp_set_stream_attribute()
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| /drivers/gpu/drm/amd/display/dc/link/hwss/ |
| A D | link_hwss_hpo_dp.c | 61 timing->h_total - timing->h_addressable), in set_hpo_dp_hblank_min_symbol_width()
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| /drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
| A D | dcn10_optc.c | 207 patched_crtc_timing.h_addressable - in optc1_program_timing()
604 h_blank = (timing->h_total - timing->h_addressable - in optc1_validate_timing()
1318 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); in optc1_get_hw_timing()
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| /drivers/gpu/drm/amd/display/dc/opp/dcn10/ |
| A D | dcn10_opp.c | 330 uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right; in opp1_program_stereo()
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_translation_helper.c | 756 …out->HActive[location] = in->timing.h_addressable + in->timing.h_border_left + in->timing.h_border… in populate_dml_timing_cfg_from_stream_state()
768 - in->timing.h_addressable in populate_dml_timing_cfg_from_stream_state()
894 out->SurfaceWidthY[location] = in->timing.h_addressable; in populate_dummy_dml_surface_cfg()
896 out->SurfaceWidthC[location] = in->timing.h_addressable; in populate_dummy_dml_surface_cfg()
1009 if (in->timing.h_addressable > 3840) in populate_dummy_dml_plane_cfg()
1012 width = in->timing.h_addressable; // 4K max in populate_dummy_dml_plane_cfg()
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| A D | dml2_utils.c | 245 hactive = timing->h_addressable + timing->h_border_left + timing->h_border_right; in populate_pipe_ctx_dlg_params_from_dml()
250 hblank_end = hblank_start - timing->h_addressable - timing->h_border_left - timing->h_border_right; in populate_pipe_ctx_dlg_params_from_dml()
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| /drivers/gpu/drm/amd/display/dc/dsc/ |
| A D | dc_dsc.c | 79 overhead_factor = dc_fixpt_from_int(timing->h_addressable); in apply_128b_132b_stream_overhead()
663 …dc_fixpt_div_int(dc_fixpt_from_int(timing->h_addressable + timing->h_border_left + timing->h_borde… in get_min_dsc_slice_count_for_odm()
1071 pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right; in setup_dsc_config()
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc_spl_translate.c | 131 …stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe… in translate_SPL_in_params_from_pipe_ctx()
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| A D | dc_hw_types.h | 902 uint32_t h_addressable; member
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| /drivers/gpu/drm/amd/display/dc/hwss/dce60/ |
| A D | dce60_hwseq.c | 126 params.source_view_width = pipe_ctx->stream->timing.h_addressable; in dce60_enable_fbc()
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| /drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| A D | dcn10_stream_encoder.c | 427 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; in enc1_stream_encoder_dp_set_stream_attribute()
459 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, in enc1_stream_encoder_dp_set_stream_attribute()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_stream_encoder.c | 462 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; in dce110_stream_encoder_dp_set_stream_attribute()
497 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, in dce110_stream_encoder_dp_set_stream_attribute()
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| /drivers/gpu/drm/amd/display/dc/dce120/ |
| A D | dce120_timing_generator.c | 440 uint32_t h_sync_start = timing->h_addressable + hsync_offset; in dce120_timing_generator_program_blanking()
468 tmp2 = tmp1 + timing->h_addressable + in dce120_timing_generator_program_blanking()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| A D | dcn314_hwseq.c | 103 …dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.… in update_dsc_on_stream()
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