| /drivers/gpu/drm/amd/display/dc/hpo/dcn31/ |
| A D | dcn31_hpo_dp_stream_encoder.c | 351 hw_crtc_timing.h_sync_width; in dcn31_hpo_dp_stream_enc_set_stream_attribute()
354 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; in dcn31_hpo_dp_stream_enc_set_stream_attribute()
422 MSA_DATA_LANE_0, hsp | (hw_crtc_timing.h_sync_width >> 8), in dcn31_hpo_dp_stream_enc_set_stream_attribute()
428 MSA_DATA_LANE_0, hw_crtc_timing.h_sync_width & 0xff, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
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| /drivers/gpu/drm/amd/display/dc/dio/dcn401/ |
| A D | dcn401_dio_stream_encoder.c | 671 hw_crtc_timing.h_sync_width; in enc401_stream_encoder_dp_set_stream_attribute()
674 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; in enc401_stream_encoder_dp_set_stream_attribute()
689 hw_crtc_timing.h_sync_width, in enc401_stream_encoder_dp_set_stream_attribute()
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| /drivers/video/fbdev/ |
| A D | acornfb.c | 122 vidc.h_sync_width = var->hsync_len - 8; in acornfb_set_timing()
123 vidc.h_border_start = vidc.h_sync_width + var->left_margin + 8 - 12; in acornfb_set_timing()
164 vidc_writel(0x81000000 | vidc.h_sync_width); in acornfb_set_timing()
226 printk(KERN_DEBUG " H-sync-width : %d\n", vidc.h_sync_width); in acornfb_set_timing()
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| A D | acornfb.h | 59 u_int h_sync_width; member
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| /drivers/gpu/drm/amd/display/dc/optc/dcn201/ |
| A D | dcn201_optc.c | 106 if (timing->h_sync_width < optc1->min_h_sync_width || in optc201_validate_timing()
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| /drivers/gpu/drm/amd/display/include/ |
| A D | bios_parser_types.h | 177 uint32_t h_sync_width; member
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| A D | dml_top_display_cfg_types.h | 251 unsigned long h_sync_width; member
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| /drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| A D | dcn10_stream_encoder.c | 430 hw_crtc_timing.h_sync_width; in enc1_stream_encoder_dp_set_stream_attribute()
433 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; in enc1_stream_encoder_dp_set_stream_attribute()
448 hw_crtc_timing.h_sync_width, in enc1_stream_encoder_dp_set_stream_attribute()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_stream_encoder.c | 465 hw_crtc_timing.h_sync_width; in dce110_stream_encoder_dp_set_stream_attribute()
468 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; in dce110_stream_encoder_dp_set_stream_attribute()
485 hw_crtc_timing.h_sync_width, in dce110_stream_encoder_dp_set_stream_attribute()
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| /drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
| A D | dcn10_optc.c | 198 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); in optc1_program_timing()
633 if (timing->h_sync_width < optc1->min_h_sync_width || in optc1_validate_timing()
1320 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start; in optc1_get_hw_timing()
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| /drivers/gpu/drm/tegra/ |
| A D | hdmi.c | 1210 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey; in tegra_hdmi_encoder_enable() local
1236 h_sync_width = mode->hsync_end - mode->hsync_start; in tegra_hdmi_encoder_enable()
1265 pulse_start = 1 + h_sync_width + h_back_porch - 10; in tegra_hdmi_encoder_enable()
1317 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch + in tegra_hdmi_encoder_enable()
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| /drivers/gpu/drm/gma500/ |
| A D | psb_intel_sdvo_regs.h | 78 u8 h_sync_width; /**< lower 8 bits (pixels) */ member
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| A D | psb_intel_sdvo.c | 783 dtd->part2.h_sync_width = h_sync_len & 0xff; in psb_intel_sdvo_get_dtd_from_mode()
808 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; in psb_intel_sdvo_get_mode_from_dtd()
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_sdvo_regs.h | 89 u8 h_sync_width; /* lower 8 bits (pixels) */ member
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| A D | intel_sdvo.c | 865 dtd->part2.h_sync_width = h_sync_len & 0xff; in intel_sdvo_get_dtd_from_mode()
892 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; in intel_sdvo_get_mode_from_dtd()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_timing_generator.c | 316 bp_params.h_sync_width = patched_crtc_timing.h_sync_width; in dce110_timing_generator_program_timing_generator()
1161 timing->h_sync_width); in dce110_timing_generator_validate_timing()
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| A D | dce110_timing_generator_v.c | 325 timing->h_sync_width, in dce110_timing_generator_v_program_blanking()
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc_hw_types.h | 918 uint32_t h_sync_width; member
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/ |
| A D | dml2_pmo_dcn3.c | 261 (timing->h_sync_width % denominator == 0); in is_h_timing_divisible_by()
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| A D | dml2_pmo_dcn4_fams2.c | 723 (timing->h_sync_width % denominator == 0); in is_h_timing_divisible_by()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_translation_helper.c | 438 timing->h_sync_width = stream->timing.h_sync_width; in populate_dml21_timing_config_from_stream_state()
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| /drivers/gpu/drm/amd/display/dc/bios/ |
| A D | command_table.c | 1838 params.usH_SyncWidth = cpu_to_le16((uint16_t)(bp_params->h_sync_width)); in set_crtc_timing_v1()
1923 params.usH_SyncWidth = cpu_to_le16((uint16_t)bp_params->h_sync_width); in set_crtc_using_dtd_timing_v3()
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| A D | command_table2.c | 636 params.h_syncwidth = cpu_to_le16((uint16_t)bp_params->h_sync_width); in set_crtc_using_dtd_timing_v3()
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| /drivers/gpu/drm/amd/display/dc/dce120/ |
| A D | dce120_timing_generator.c | 121 timing->h_sync_width < tg110->min_h_sync_width || in dce120_timing_generator_validate_timing()
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| /drivers/gpu/drm/amd/include/ |
| A D | atomfirmware.h | 444 uint16_t h_sync_width; member
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