Home
last modified time | relevance | path

Searched refs:h_taps (Results 1 – 25 of 27) sorted by relevance

12

/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
A Ddcn201_dpp.c218 if (in_taps->h_taps == 0) { in dpp201_get_optimal_number_of_taps()
220 scl_data->taps.h_taps = 8; in dpp201_get_optimal_number_of_taps()
222 scl_data->taps.h_taps = 4; in dpp201_get_optimal_number_of_taps()
224 scl_data->taps.h_taps = in_taps->h_taps; in dpp201_get_optimal_number_of_taps()
253 scl_data->taps.h_taps = 1; in dpp201_get_optimal_number_of_taps()
/drivers/gpu/drm/amd/display/dc/sspl/
A Ddc_spl.c675 spl_scratch->scl_data.taps.h_taps, in spl_calculate_inits_and_viewports()
883 if ((taps.h_taps == 4 || taps.h_taps == 6) && in spl_get_isharp_en()
898 if (in_taps->h_taps == 0) { in spl_get_taps_non_adaptive_scaler()
903 spl_scratch->scl_data.taps.h_taps = 4; in spl_get_taps_non_adaptive_scaler()
905 spl_scratch->scl_data.taps.h_taps = in_taps->h_taps; in spl_get_taps_non_adaptive_scaler()
956 spl_scratch->scl_data.taps.h_taps = 1; in spl_get_taps_non_adaptive_scaler()
1011 spl_scratch->scl_data.taps.h_taps = 6; in spl_get_optimal_number_of_taps()
1016 spl_scratch->scl_data.taps.h_taps = 6; in spl_get_optimal_number_of_taps()
1085 spl_scratch->scl_data.taps.h_taps = 4; in spl_get_optimal_number_of_taps()
1218 dscl_prog_data->taps.h_taps = scl_data->taps.h_taps - 1; in spl_set_taps_data()
[all …]
A Ddc_spl_scl_easf_filters.c2355 data->taps.h_taps, data->recip_ratios.horz); in spl_set_filters_data()
2361 data->taps.h_taps, data->ratios.horz); in spl_set_filters_data()
A Ddc_spl_isharp_filters.c548 spl_dscl_get_blur_scale_coeffs_64p(data->taps.h_taps); in spl_set_blur_scale_data()
A Ddc_spl_types.h39 uint32_t h_taps; member
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_transform.c122 if (data->taps.h_taps + data->taps.v_taps <= 2) { in setup_scaling_configuration()
132 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, in setup_scaling_configuration()
156 if (data->taps.h_taps + data->taps.v_taps <= 2) { in dce60_setup_scaling_configuration()
165 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, in dce60_setup_scaling_configuration()
294 dc_fixpt_from_int(data->taps.h_taps + 1)), in calculate_inits()
440 coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz); in dce_transform_set_scaler()
464 data->taps.h_taps, in dce_transform_set_scaler()
469 data->taps.h_taps, in dce_transform_set_scaler()
549 data->taps.h_taps, in dce60_transform_set_scaler()
554 data->taps.h_taps, in dce60_transform_set_scaler()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_display_cfg_types.h229 unsigned int h_taps; member
236 unsigned int h_taps; member
297 unsigned long h_taps; member
/drivers/gpu/drm/amd/display/dc/
A Ddc_spl_translate.c37 spl_scaling_quality->h_taps = scaling_quality->h_taps; in populate_spltaps_from_taps()
46 scaling_quality->h_taps = spl_scaling_quality->h_taps + 1; in populate_taps_from_spltaps()
A Ddc_hw_types.h713 uint32_t h_taps; member
/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
A Ddcn10_dpp.c154 if (in_taps->h_taps == 0) in dpp1_get_optimal_number_of_taps()
155 scl_data->taps.h_taps = 4; in dpp1_get_optimal_number_of_taps()
157 scl_data->taps.h_taps = in_taps->h_taps; in dpp1_get_optimal_number_of_taps()
176 scl_data->taps.h_taps = 1; in dpp1_get_optimal_number_of_taps()
A Ddcn10_dpp_dscl.c295 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 in dpp1_dscl_set_scl_filter()
297 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp1_dscl_set_scl_filter()
317 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp1_dscl_set_scl_filter()
338 dpp, scl_data->taps.h_taps, in dpp1_dscl_set_scl_filter()
690 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, in dpp1_dscl_set_scaler_manual_scale()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c768 plane->composition.scaler_info.plane0.h_taps = 1; in populate_dml21_dummy_plane_cfg()
770 plane->composition.scaler_info.plane1.h_taps = 0; in populate_dml21_dummy_plane_cfg()
897 if (!scaler_data->taps.h_taps) { in populate_dml21_plane_config_from_plane_state()
907 if ((scaler_data->taps.h_taps > 1) || (scaler_data->taps.v_taps > 1) || in populate_dml21_plane_config_from_plane_state()
930 if (!scaler_data->taps.h_taps) { in populate_dml21_plane_config_from_plane_state()
931 plane->composition.scaler_info.plane0.h_taps = 1; in populate_dml21_plane_config_from_plane_state()
932 plane->composition.scaler_info.plane1.h_taps = 1; in populate_dml21_plane_config_from_plane_state()
934 plane->composition.scaler_info.plane0.h_taps = scaler_data->taps.h_taps; in populate_dml21_plane_config_from_plane_state()
935 plane->composition.scaler_info.plane1.h_taps = scaler_data->taps.h_taps_c; in populate_dml21_plane_config_from_plane_state()
/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_transform_v.c165 set_reg_field_value(value, data->taps.h_taps - 1, in setup_scaling_configuration()
176 if (data->taps.h_taps + data->taps.v_taps > 2) { in setup_scaling_configuration()
560 coeffs_h = get_filter_coeffs_64p(data->taps.h_taps, data->ratios.horz); in dce110_xfmv_set_scaler()
583 data->taps.h_taps, in dce110_xfmv_set_scaler()
/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
A Ddcn401_dpp_dscl.c307 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp401_dscl_set_scl_filter()
318 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 in dpp401_dscl_set_scl_filter()
320 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp401_dscl_set_scl_filter()
352 dpp, scl_data->taps.h_taps, in dpp401_dscl_set_scl_filter()
1044 dpp, scl_data->taps.h_taps, in dpp401_dscl_program_isharp()
1072 uint32_t h_num_taps = scl_data->taps.h_taps - 1; in dpp401_dscl_set_scaler_manual_scale()
1111 h_num_taps = scl_data->dscl_prog_data.taps.h_taps; in dpp401_dscl_set_scaler_manual_scale()
/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
A Ddcn30_dpp.c433 if (in_taps->h_taps == 0) { in dpp3_get_optimal_number_of_taps()
435 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8); in dpp3_get_optimal_number_of_taps()
437 scl_data->taps.h_taps = 4; in dpp3_get_optimal_number_of_taps()
439 scl_data->taps.h_taps = in_taps->h_taps; in dpp3_get_optimal_number_of_taps()
508 scl_data->taps.h_taps = 1; in dpp3_get_optimal_number_of_taps()
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_debug.c166 update->scaling_info->scaling_quality.h_taps, in update_surface_trace()
A Ddc_resource.c1297 data->taps.h_taps, in calculate_inits_and_viewports()
1575 pipe_ctx->plane_res.scl_data.taps.h_taps != temp.h_taps || in resource_build_scaling_params()
/drivers/gpu/drm/amd/display/dc/basics/
A Ddce_calcs.c380 data->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); in calculate_bandwidth()
381 data->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); in calculate_bandwidth()
434 data->h_taps[i] = bw_int_to_fixed(1); in calculate_bandwidth()
524 if (bw_mtn(data->hsr[i], data->h_taps[i])) { in calculate_bandwidth()
528 …sr[i], bw_int_to_fixed(1)) && bw_leq(data->hsr[i], bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixe… in calculate_bandwidth()
1704 …data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_t… in calculate_bandwidth()
2828 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2884 …data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
2931 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2983 …data->h_taps[num_displays + 4] = pipe[i].stream->src.width == pipe[i].stream->dst.width ? bw_int_t… in populate_initial_data()
[all …]
A Dcalcs_logger.h430 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_taps[%d]:%d", i, bw_fixed_to_int(data->h_taps[i])); in print_bw_calcs_data()
/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_dwb_scl.c728 uint32_t h_taps_luma = num_taps.h_taps; in dwb_program_horz_scalar()
/drivers/gpu/drm/amd/display/dc/inc/
A Ddce_calcs.h396 struct bw_fixed h_taps[maximum_number_of_surfaces]; member
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_translation_helper.c1105 if (!scaler_data->taps.h_taps) { in populate_dml_plane_cfg_from_plane_state()
1109 out->HTaps[location] = scaler_data->taps.h_taps; in populate_dml_plane_cfg_from_plane_state()
1247 out->WritebackHTaps[location] = wb_info->dwb_params.scaler_taps.h_taps > 0 ? in populate_dml_writeback_cfg_from_stream_state()
1248 wb_info->dwb_params.scaler_taps.h_taps : 1; in populate_dml_writeback_cfg_from_stream_state()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_dcn4_calcs.c8001 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps != 1.0 in dml_core_mode_support()
8006 …].composition.scaler_info.plane0.h_taps < 1.0 || display_cfg->plane_descriptors[k].composition.sca… in dml_core_mode_support()
8007 ….composition.scaler_info.plane0.h_taps > 1.0 && (display_cfg->plane_descriptors[k].composition.sca… in dml_core_mode_support()
8014 …k].composition.scaler_info.plane1.h_taps < 1 || display_cfg->plane_descriptors[k].composition.scal… in dml_core_mode_support()
8015 …k].composition.scaler_info.plane1.h_taps > 1 && display_cfg->plane_descriptors[k].composition.scal… in dml_core_mode_support()
8123 …tream[0].h_taps > 2.0 && ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].strea… in dml_core_mode_support()
8142 display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps, in dml_core_mode_support()
8143 display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps, in dml_core_mode_support()
8560 …m_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps, in dml_core_mode_support()
10491 display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps, in dml_core_mode_programming()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
1012 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; in dcn_validate_bandwidth()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c219 dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps; in dcn30_fpu_populate_dml_writeback_from_context()

Completed in 141 milliseconds

12