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/drivers/gpu/drm/tve200/
A Dtve200_display.c82 if (!(mode->hdisplay == 352 && mode->vdisplay == 240) && /* SIF(525) */ in tve200_display_check()
83 !(mode->hdisplay == 352 && mode->vdisplay == 288) && /* CIF(625) */ in tve200_display_check()
84 !(mode->hdisplay == 640 && mode->vdisplay == 480) && /* VGA */ in tve200_display_check()
85 !(mode->hdisplay == 720 && mode->vdisplay == 480) && /* D1 */ in tve200_display_check()
86 !(mode->hdisplay == 720 && mode->vdisplay == 576)) { /* D1 */ in tve200_display_check()
88 mode->hdisplay, mode->vdisplay); in tve200_display_check()
105 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) { in tve200_display_check()
171 if ((mode->hdisplay == 352 && mode->vdisplay == 240) || /* SIF(525) */ in tve200_display_enable()
175 } else if (mode->hdisplay == 640 && mode->vdisplay == 480) { in tve200_display_enable()
178 } else if ((mode->hdisplay == 720 && mode->vdisplay == 480) || in tve200_display_enable()
[all …]
/drivers/gpu/drm/panel/
A Dpanel-simple.c800 .hdisplay = 1280,
826 .hdisplay = 480,
850 .hdisplay = 800,
1093 .hdisplay = 800,
1117 .hdisplay = 800,
1418 .hdisplay = 800,
1626 .hdisplay = 480,
1678 .hdisplay = 800,
1704 .hdisplay = 800,
1757 .hdisplay = 800,
[all …]
A Dpanel-edp.c1016 .hdisplay = 1366,
1029 .hdisplay = 1366,
1057 .hdisplay = 1920,
1084 .hdisplay = 1366,
1191 .hdisplay = 1920,
1261 .hdisplay = 1366,
1323 .hdisplay = 1920,
1345 .hdisplay = 2160,
1372 .hdisplay = 1366,
1398 .hdisplay = 1536,
[all …]
A Dpanel-sharp-lq101r1sx01.c113 err = mipi_dsi_dcs_set_column_address(left, 0, mode->hdisplay / 2 - 1); in sharp_setup_symmetrical_split()
125 err = mipi_dsi_dcs_set_column_address(right, mode->hdisplay / 2, in sharp_setup_symmetrical_split()
126 mode->hdisplay - 1); in sharp_setup_symmetrical_split()
227 .hdisplay = 2560,
245 default_mode.hdisplay, default_mode.vdisplay, in sharp_panel_get_modes()
A Dpanel-arm-versatile.c138 .hdisplay = 320,
161 .hdisplay = 640,
183 .hdisplay = 176,
206 .hdisplay = 240,
/drivers/gpu/drm/ast/
A Dast_vbios.c184 unsigned int hdisplay, in __ast_vbios_find_mode_table() argument
188 if ((*vmode_tables)->hde == hdisplay && (*vmode_tables)->vde == vdisplay) in __ast_vbios_find_mode_table()
197 unsigned int hdisplay, in ast_vbios_find_mode_table() argument
203 vmode_table = __ast_vbios_find_mode_table(res_table_wuxga, hdisplay, vdisplay); in ast_vbios_find_mode_table()
205 vmode_table = __ast_vbios_find_mode_table(res_table_fullhd, hdisplay, vdisplay); in ast_vbios_find_mode_table()
207 vmode_table = __ast_vbios_find_mode_table(res_table_wsxga_p, hdisplay, vdisplay); in ast_vbios_find_mode_table()
209 vmode_table = __ast_vbios_find_mode_table(res_table, hdisplay, vdisplay); in ast_vbios_find_mode_table()
222 vmode_table = ast_vbios_find_mode_table(ast, mode->hdisplay, mode->vdisplay); in ast_vbios_find_mode()
A Dast_dp.c19 unsigned int hdisplay; member
58 static int ast_astdp_get_mode_index(unsigned int hdisplay, unsigned int vdisplay) in ast_astdp_get_mode_index() argument
62 while (entry->hdisplay && entry->vdisplay) { in ast_astdp_get_mode_index()
63 if (entry->hdisplay == hdisplay && entry->vdisplay == vdisplay) in ast_astdp_get_mode_index()
309 res = ast_astdp_get_mode_index(mode->hdisplay, mode->vdisplay); in ast_astdp_encoder_helper_mode_valid()
395 res = ast_astdp_get_mode_index(mode->hdisplay, mode->vdisplay); in ast_astdp_encoder_helper_atomic_check()
/drivers/gpu/drm/
A Ddrm_modes.c456 mode->hdisplay = hactive; in fill_analog_mode()
548 unsigned int hdisplay, in drm_analog_tv_mode() argument
644 if (!hdisplay || !vdisplay) in drm_cvt_mode()
665 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); in drm_cvt_mode()
882 if (!hdisplay || !vdisplay) in drm_gtf_mode_complex()
1074 dmode->hdisplay = vm->hactive; in drm_display_mode_from_videomode()
1475 return mode1->hdisplay == mode2->hdisplay && in drm_mode_match_timings()
1643 if (mode->hdisplay == 0 || in drm_mode_validate_basic()
1852 diff = b->hdisplay * b->vdisplay - a->hdisplay * a->vdisplay; in drm_mode_compare()
2586 out->hdisplay = in->hdisplay; in drm_mode_convert_to_umode()
[all …]
/drivers/gpu/drm/nouveau/dispnv04/
A Dtvnv17.c222 if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay && in nv17_tv_get_ld_modes()
240 int hdisplay; in nv17_tv_get_hd_modes() member
256 if (modes[i].hdisplay > output_mode->hdisplay || in nv17_tv_get_hd_modes()
260 if (modes[i].hdisplay == output_mode->hdisplay && in nv17_tv_get_hd_modes()
268 mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay, in nv17_tv_get_hd_modes()
277 if (output_mode->hdisplay <= 720 in nv17_tv_get_hd_modes()
278 || output_mode->hdisplay >= 1920) { in nv17_tv_get_hd_modes()
280 mode->hsync_start = (mode->hdisplay + (mode->htotal in nv17_tv_get_hd_modes()
281 - mode->hdisplay) * 9 / 10) & ~7; in nv17_tv_get_hd_modes()
322 if (mode->hdisplay > output_mode->hdisplay || in nv17_tv_mode_valid()
[all …]
A Ddfp.c192 mode->hdisplay > nv_connector->native_mode->hdisplay || in nv04_dfp_mode_fixup()
301 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; in nv04_dfp_mode_set()
304 (output_mode->hsync_start - output_mode->hdisplay) >= in nv04_dfp_mode_set()
306 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay; in nv04_dfp_mode_set()
312 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1; in nv04_dfp_mode_set()
335 else if (adjusted_mode->hdisplay == output_mode->hdisplay && in nv04_dfp_mode_set()
375 mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay; in nv04_dfp_mode_set()
376 panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay; in nv04_dfp_mode_set()
394 diff = output_mode->hdisplay - in nv04_dfp_mode_set()
405 scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay; in nv04_dfp_mode_set()
[all …]
A Dtvmodesnv17.c324 uint64_t rs[] = {mode->hdisplay * id3, in tv_setup_filter()
327 do_div(rs[0], overscan * tv_norm->tv_enc_mode.hdisplay); in tv_setup_filter()
558 hmargin = (output_mode->hdisplay - crtc_mode->hdisplay) / 2; in nv17_ctv_update_rescaler()
561 hmargin = interpolate(0, min(hmargin, output_mode->hdisplay/20), in nv17_ctv_update_rescaler()
566 hratio = crtc_mode->hdisplay * 0x800 / in nv17_ctv_update_rescaler()
567 (output_mode->hdisplay - 2*hmargin); in nv17_ctv_update_rescaler()
572 regs->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - hmargin - 1; in nv17_ctv_update_rescaler()
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_encoders.c169 unsigned int hblank = native_mode->htotal - native_mode->hdisplay; in amdgpu_panel_mode_fixup()
171 unsigned int hover = native_mode->hsync_start - native_mode->hdisplay; in amdgpu_panel_mode_fixup()
179 adjusted_mode->hdisplay = native_mode->hdisplay; in amdgpu_panel_mode_fixup()
182 adjusted_mode->htotal = native_mode->hdisplay + hblank; in amdgpu_panel_mode_fixup()
183 adjusted_mode->hsync_start = native_mode->hdisplay + hover; in amdgpu_panel_mode_fixup()
192 adjusted_mode->crtc_hdisplay = native_mode->hdisplay; in amdgpu_panel_mode_fixup()
A Damdgpu_connectors.c363 if (native_mode->hdisplay != 0 && in amdgpu_connector_lcd_native_mode()
374 } else if (native_mode->hdisplay != 0 && in amdgpu_connector_lcd_native_mode()
431 if (common_modes[i].w > native_mode->hdisplay || in amdgpu_connector_add_common_modes()
433 (common_modes[i].w == native_mode->hdisplay && in amdgpu_connector_add_common_modes()
614 if (mode->hdisplay != native_mode->hdisplay || in amdgpu_connector_fixup_lcd_native_mode()
623 if (mode->hdisplay == native_mode->hdisplay && in amdgpu_connector_fixup_lcd_native_mode()
681 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) in amdgpu_connector_lvds_mode_valid()
691 if ((mode->hdisplay > native_mode->hdisplay) || in amdgpu_connector_lvds_mode_valid()
697 if ((mode->hdisplay != native_mode->hdisplay) || in amdgpu_connector_lvds_mode_valid()
1488 if ((mode->hdisplay > native_mode->hdisplay) || in amdgpu_connector_dp_mode_valid()
[all …]
/drivers/gpu/drm/radeon/
A Dradeon_encoders.c327 unsigned int hblank = native_mode->htotal - native_mode->hdisplay; in radeon_panel_mode_fixup()
329 unsigned int hover = native_mode->hsync_start - native_mode->hdisplay; in radeon_panel_mode_fixup()
338 adjusted_mode->hdisplay = native_mode->hdisplay; in radeon_panel_mode_fixup()
342 adjusted_mode->htotal = native_mode->hdisplay + hblank; in radeon_panel_mode_fixup()
343 adjusted_mode->hsync_start = native_mode->hdisplay + hover; in radeon_panel_mode_fixup()
353 adjusted_mode->crtc_hdisplay = native_mode->hdisplay; in radeon_panel_mode_fixup()
/drivers/gpu/drm/hisilicon/hibmc/dp/
A Ddp_hw.c63 hblank_int = mode->htotal - mode->hdisplay - mode->hdisplay * 53 / 10000; in hibmc_dp_set_sst()
68 mode->hdisplay, mode->vdisplay, htotal_size, hblank_size); in hibmc_dp_set_sst()
93 HIBMC_DP_CFG_TIMING_GEN0_HBLANK, mode->htotal - mode->hdisplay); in hibmc_dp_link_cfg()
95 HIBMC_DP_CFG_TIMING_GEN0_HACTIVE, mode->hdisplay); in hibmc_dp_link_cfg()
106 HIBMC_DP_CFG_STREAM_HACTIVE, mode->hdisplay); in hibmc_dp_link_cfg()
108 HIBMC_DP_CFG_STREAM_HBLANK, mode->htotal - mode->hdisplay); in hibmc_dp_link_cfg()
/drivers/gpu/drm/gma500/
A Doaktrail_lvds.c135 (mode->hdisplay != adjusted_mode->crtc_hdisplay)) { in oaktrail_lvds_mode_set()
137 (mode->hdisplay * adjusted_mode->crtc_vdisplay)) in oaktrail_lvds_mode_set()
140 mode->vdisplay) > (mode->hdisplay * in oaktrail_lvds_mode_set()
229 mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo; in oaktrail_lvds_get_configuration_mode()
231 mode->hsync_start = mode->hdisplay + \ in oaktrail_lvds_get_configuration_mode()
237 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \ in oaktrail_lvds_get_configuration_mode()
249 pr_info("hdisplay is %d\n", mode->hdisplay); in oaktrail_lvds_get_configuration_mode()
A Dcdv_intel_lvds.c172 if (mode->hdisplay > fixed_mode->hdisplay) in cdv_intel_lvds_mode_valid()
207 adjusted_mode->hdisplay = panel_fixed_mode->hdisplay; in cdv_intel_lvds_mode_fixup()
280 if (mode->hdisplay != adjusted_mode->hdisplay || in cdv_intel_lvds_mode_set()
372 if (crtc->saved_mode.hdisplay != 0 && in cdv_intel_lvds_set_property()
/drivers/gpu/drm/i915/display/
A Dintel_tv.c1008 mode->hdisplay = in intel_tv_mode_to_mode()
1010 mode->hsync_start = mode->hdisplay + in intel_tv_mode_to_mode()
1051 mode->hdisplay, mode->vdisplay, in intel_tv_mode_to_mode()
1057 int hdisplay, int left_margin, in intel_tv_scale_mode_horiz() argument
1062 int new_htotal = mode->htotal * hdisplay / in intel_tv_scale_mode_horiz()
1067 mode->hdisplay = hdisplay; in intel_tv_scale_mode_horiz()
1100 int hdisplay = adjusted_mode->crtc_hdisplay; in intel_tv_get_config() local
1158 intel_tv_scale_mode_horiz(&mode, hdisplay, in intel_tv_get_config()
1159 xpos, mode.hdisplay - xsize - xpos); in intel_tv_get_config()
1174 int hdisplay) in intel_tv_source_too_wide() argument
[all …]
A Ddvo_ns2501.c532 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal); in ns2501_mode_valid()
540 if ((mode->hdisplay == 640 && mode->vdisplay == 480 && mode->clock == 25175) || in ns2501_mode_valid()
541 (mode->hdisplay == 800 && mode->vdisplay == 600 && mode->clock == 40000) || in ns2501_mode_valid()
542 (mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 65000)) { in ns2501_mode_valid()
559 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal); in ns2501_mode_set()
591 if (mode->hdisplay == 640 && mode->vdisplay == 480) in ns2501_mode_set()
593 else if (mode->hdisplay == 800 && mode->vdisplay == 600) in ns2501_mode_set()
595 else if (mode->hdisplay == 1024 && mode->vdisplay == 768) in ns2501_mode_set()
/drivers/gpu/drm/gud/
A Dgud_internal.h135 dst->hdisplay = cpu_to_le16(src->hdisplay); in gud_from_display_mode()
153 dst->hdisplay = le16_to_cpu(src->hdisplay); in gud_to_display_mode()
/drivers/gpu/drm/bridge/
A Dti-dlpc3433.c136 buf[4] = mode->hdisplay & 0xff; in dlpc_atomic_enable()
137 buf[5] = (mode->hdisplay & 0xff00) >> 8; in dlpc_atomic_enable()
143 buf[4] = mode->hdisplay & 0xff; in dlpc_atomic_enable()
144 buf[5] = (mode->hdisplay & 0xff00) >> 8; in dlpc_atomic_enable()
150 buf[0] = mode->hdisplay & 0xff; in dlpc_atomic_enable()
151 buf[1] = (mode->hdisplay & 0xff00) >> 8; in dlpc_atomic_enable()
/drivers/gpu/drm/imx/lcdc/
A Dimx-lcdc.c161 framesize = FIELD_PREP(IMX21LCDC_LSR_XMAX, crtc->mode.hdisplay >> 4) | in imx_lcdc_update_hw_registers()
166 lhcr = FIELD_PREP(IMX21LCDC_LHCR_HFPORCH, crtc->mode.hsync_start - crtc->mode.hdisplay - 1) | in imx_lcdc_update_hw_registers()
282 if (mode->hdisplay < LCDC_MIN_XRES || mode->hdisplay > LCDC_MAX_XRES || in imx_lcdc_pipe_check()
284 mode->hdisplay % 0x10) { /* must be multiple of 16 */ in imx_lcdc_pipe_check()
286 mode->hdisplay, mode->vdisplay); in imx_lcdc_pipe_check()
291 old_mode->hdisplay != mode->hdisplay || in imx_lcdc_pipe_check()
/drivers/gpu/drm/pl111/
A Dpl111_display.c64 bw = bw * mode->hdisplay * mode->vdisplay * cpp; in pl111_mode_valid()
73 mode->hdisplay, mode->vdisplay, in pl111_mode_valid()
79 mode->hdisplay, mode->vdisplay, in pl111_mode_valid()
93 if (mode->hdisplay % 16) in pl111_display_check()
106 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) in pl111_display_check()
147 ppl = (mode->hdisplay / 16) - 1; in pl111_display_enable()
149 hfp = mode->hsync_start - mode->hdisplay - 1; in pl111_display_enable()
157 cpl = mode->hdisplay - 1; in pl111_display_enable()
/drivers/gpu/drm/vc4/
A Dvc4_txp.c203 int w = mode->hdisplay, h = mode->vdisplay; in vc4_txp_connector_mode_valid()
262 if (fb->width != crtc_state->mode.hdisplay || in vc4_txp_connector_atomic_check()
297 unsigned int hdisplay; in vc4_txp_connector_atomic_commit() local
346 hdisplay = mode->hdisplay ?: 1; in vc4_txp_connector_atomic_commit()
349 hdisplay -= 1; in vc4_txp_connector_atomic_commit()
354 VC4_SET_FIELD(hdisplay, TXP_WIDTH) | in vc4_txp_connector_atomic_commit()
/drivers/gpu/drm/tilcdc/
A Dtilcdc_plane.c51 if (crtc_state->mode.hdisplay != new_state->crtc_w || in tilcdc_plane_atomic_check()
55 crtc_state->mode.hdisplay, crtc_state->mode.vdisplay, in tilcdc_plane_atomic_check()
60 pitch = crtc_state->mode.hdisplay * in tilcdc_plane_atomic_check()

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