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Searched refs:hdmi_pll_write (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/msm/hdmi/
A Dhdmi_phy_8996.c417 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_CTRL, 0x04); in hdmi_8996_pll_set_clk_rate()
451 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_TRIM, 0x0F); in hdmi_8996_pll_set_clk_rate()
453 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL, in hdmi_8996_pll_set_clk_rate()
456 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_CTRL, 0x06); in hdmi_8996_pll_set_clk_rate()
459 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL, in hdmi_8996_pll_set_clk_rate()
461 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN, in hdmi_8996_pll_set_clk_rate()
468 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0, in hdmi_8996_pll_set_clk_rate()
492 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN, in hdmi_8996_pll_set_clk_rate()
494 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV, in hdmi_8996_pll_set_clk_rate()
614 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_PER1, 0x0); in hdmi_8996_pll_prepare()
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A Dhdmi_phy_8998.c489 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_PLL_IVCO, 0x07); in hdmi_8998_pll_set_clk_rate()
492 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CLK_SEL, 0x30); in hdmi_8998_pll_set_clk_rate()
493 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_HSCLK_SEL, in hdmi_8998_pll_set_clk_rate()
495 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP_EN, in hdmi_8998_pll_set_clk_rate()
498 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_PLL_CCTRL_MODE0, in hdmi_8998_pll_set_clk_rate()
500 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_PLL_RCTRL_MODE0, in hdmi_8998_pll_set_clk_rate()
502 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CP_CTRL_MODE0, in hdmi_8998_pll_set_clk_rate()
504 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DEC_START_MODE0, in hdmi_8998_pll_set_clk_rate()
518 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP1_MODE0, in hdmi_8998_pll_set_clk_rate()
520 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP2_MODE0, in hdmi_8998_pll_set_clk_rate()
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