Searched refs:hdr_mult (Results 1 – 12 of 12) sorted by relevance
| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_plane.c | 1475 amdgpu_state->hdr_mult = AMDGPU_HDR_MULT_DEFAULT; in amdgpu_dm_plane_drm_plane_reset()
1513 dm_plane_state->hdr_mult = old_dm_plane_state->hdr_mult; in amdgpu_dm_plane_drm_plane_duplicate_state()
1689 if (dm_plane_state->hdr_mult != val) { in dm_atomic_plane_set_property()
1690 dm_plane_state->hdr_mult = val; in dm_atomic_plane_set_property()
1761 *val = dm_plane_state->hdr_mult; in dm_atomic_plane_get_property()
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| A D | amdgpu_dm_color.c | 1151 dc_plane_state->hdr_mult = amdgpu_dm_fixpt_from_s3132(dm_plane_state->hdr_mult); in amdgpu_dm_plane_set_color_properties()
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| A D | amdgpu_dm.h | 876 __u64 hdr_mult; member
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| A D | amdgpu_dm.c | 9398 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; in amdgpu_dm_commit_planes()
10035 wb_info->dwb_params.hdr_mult = 0x1F000; in dm_set_writeback()
11157 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult || in should_reset_plane()
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| /drivers/gpu/drm/amd/display/dc/sspl/ |
| A D | dc_spl.c | 1264 struct spl_fixed31_32 hdr_mult, c0_mult, c1_mult, c2_mult; in spl_calculate_c0_c3_hdr() local
1274 hdr_mult = spl_fixpt_from_fraction((long long)hdr_multx100_int, 100LL); in spl_calculate_c0_c3_hdr()
1279 c0_calc = spl_fixpt_mul(hdr_mult, spl_fixpt_mul(c0_mult, spl_fixpt_from_fraction( in spl_calculate_c0_c3_hdr()
1281 c1_calc = spl_fixpt_mul(hdr_mult, spl_fixpt_mul(c1_mult, spl_fixpt_from_fraction( in spl_calculate_c0_c3_hdr()
1283 c2_calc = spl_fixpt_mul(hdr_mult, spl_fixpt_mul(c2_mult, spl_fixpt_from_fraction( in spl_calculate_c0_c3_hdr()
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc.h | 1342 uint32_t hdr_mult:1; member
1393 struct fixed31_32 hdr_mult; member
1764 struct fixed31_32 hdr_mult; member
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| A D | dc_types.h | 421 unsigned int hdr_mult; /* must be in FP1.6.12 */ member
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| /drivers/gpu/drm/amd/display/dc/dwb/dcn30/ |
| A D | dcn30_dwb_cm.c | 394 REG_UPDATE(DWB_HDR_MULT_COEF, DWB_HDR_MULT_COEF, params->hdr_mult); in dwb3_program_hdr_mult()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc.c | 2824 if (u->hdr_mult.value) in det_surface_update()
2825 if (u->hdr_mult.value != u->surface->hdr_mult.value) { in det_surface_update()
2826 update_flags->bits.hdr_mult = 1; in det_surface_update()
3152 if (srf_update->hdr_mult.value) in copy_surface_update_to_plane()
3153 surface->hdr_mult = in copy_surface_update_to_plane()
3154 srf_update->hdr_mult; in copy_surface_update_to_plane()
5019 (srf_updates[i].hdr_mult.value && in full_update_required()
5020 srf_updates[i].hdr_mult.value != srf_updates->surface->hdr_mult.value) || in full_update_required()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| A D | dcn401_hwseq.c | 2007 pipe_ctx->plane_state->update_flags.bits.hdr_mult)) in dcn401_program_pipe()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 1970 pipe_ctx->plane_state->update_flags.bits.hdr_mult)) in dcn20_program_pipe()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 3150 struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult; in dcn10_set_hdr_multiplier()
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