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Searched refs:high_part (Results 1 – 25 of 34) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
A Ddcn30_hubp.c118 address->grph.meta_addr.high_part); in hubp3_program_surface_flip_and_addr()
127 address->grph.addr.high_part); in hubp3_program_surface_flip_and_addr()
172 address->video_progressive.luma_addr.high_part); in hubp3_program_surface_flip_and_addr()
224 address->grph_stereo.left_meta_addr.high_part); in hubp3_program_surface_flip_and_addr()
241 address->grph_stereo.right_addr.high_part); in hubp3_program_surface_flip_and_addr()
257 address->grph_stereo.left_addr.high_part); in hubp3_program_surface_flip_and_addr()
278 address->rgbea.alpha_meta_addr.high_part); in hubp3_program_surface_flip_and_addr()
286 address->rgbea.meta_addr.high_part); in hubp3_program_surface_flip_and_addr()
295 address->rgbea.alpha_addr.high_part); in hubp3_program_surface_flip_and_addr()
303 address->rgbea.addr.high_part); in hubp3_program_surface_flip_and_addr()
[all …]
/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_dcn30.c103 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_backdoor_load()
112 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_backdoor_load()
138 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows()
153 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows()
164 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows()
171 REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows()
181 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows()
188 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows()
197 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows()
A Ddmub_dcn20.c170 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_backdoor_load()
179 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_backdoor_load()
207 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_setup_windows()
222 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_setup_windows()
234 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_setup_windows()
241 REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_setup_windows()
251 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_setup_windows()
258 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_setup_windows()
267 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_setup_windows()
A Ddmub_dcn35.c174 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn35_backdoor_load()
183 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn35_backdoor_load()
202 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn35_backdoor_load_zfb_mode()
209 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn35_backdoor_load_zfb_mode()
230 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); in dmub_dcn35_setup_windows()
239 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); in dmub_dcn35_setup_windows()
248 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn35_setup_windows()
255 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn35_setup_windows()
264 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); in dmub_dcn35_setup_windows()
273 REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part); in dmub_dcn35_setup_windows()
A Ddmub_dcn401.c143 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn401_backdoor_load()
152 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn401_backdoor_load()
177 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn401_backdoor_load_zfb_mode()
186 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn401_backdoor_load_zfb_mode()
210 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); in dmub_dcn401_setup_windows()
219 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); in dmub_dcn401_setup_windows()
228 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn401_setup_windows()
235 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn401_setup_windows()
244 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); in dmub_dcn401_setup_windows()
253 REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part); in dmub_dcn401_setup_windows()
A Ddmub_dcn32.c165 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn32_backdoor_load()
174 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn32_backdoor_load()
195 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn32_backdoor_load_zfb_mode()
204 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn32_backdoor_load_zfb_mode()
227 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); in dmub_dcn32_setup_windows()
236 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); in dmub_dcn32_setup_windows()
245 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn32_setup_windows()
252 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn32_setup_windows()
261 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); in dmub_dcn32_setup_windows()
A Ddmub_dcn31.c171 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_backdoor_load()
180 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_backdoor_load()
203 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_setup_windows()
212 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_setup_windows()
221 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_setup_windows()
228 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_setup_windows()
237 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_setup_windows()
/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
A Ddcn10_hubp.c398 address->grph.meta_addr.high_part); in hubp1_program_surface_flip_and_addr()
407 address->grph.addr.high_part); in hubp1_program_surface_flip_and_addr()
427 address->video_progressive.chroma_meta_addr.high_part); in hubp1_program_surface_flip_and_addr()
435 address->video_progressive.luma_meta_addr.high_part); in hubp1_program_surface_flip_and_addr()
444 address->video_progressive.chroma_addr.high_part); in hubp1_program_surface_flip_and_addr()
452 address->video_progressive.luma_addr.high_part); in hubp1_program_surface_flip_and_addr()
478 address->grph_stereo.right_meta_addr.high_part); in hubp1_program_surface_flip_and_addr()
488 address->grph_stereo.left_meta_addr.high_part); in hubp1_program_surface_flip_and_addr()
497 address->grph_stereo.right_addr.high_part); in hubp1_program_surface_flip_and_addr()
505 address->grph_stereo.left_addr.high_part); in hubp1_program_surface_flip_and_addr()
[all …]
/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
A Ddcn21_hubp.c718 address->grph.meta_addr.high_part; in hubp21_program_surface_flip_and_addr()
724 address->grph.addr.high_part; in hubp21_program_surface_flip_and_addr()
735 address->video_progressive.luma_meta_addr.high_part; in hubp21_program_surface_flip_and_addr()
740 address->video_progressive.chroma_meta_addr.high_part; in hubp21_program_surface_flip_and_addr()
746 address->video_progressive.luma_addr.high_part; in hubp21_program_surface_flip_and_addr()
752 address->video_progressive.chroma_addr.high_part; in hubp21_program_surface_flip_and_addr()
767 address->grph_stereo.right_meta_addr.high_part; in hubp21_program_surface_flip_and_addr()
774 address->grph_stereo.left_meta_addr.high_part; in hubp21_program_surface_flip_and_addr()
780 address->grph_stereo.left_addr.high_part; in hubp21_program_surface_flip_and_addr()
785 address->grph_stereo.right_addr.high_part; in hubp21_program_surface_flip_and_addr()
/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
A Ddcn401_hubp.c48 REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address.lut3d.addr.high_part); in hubp401_program_3dlut_fl_addr()
413 address->grph.addr.high_part); in hubp401_program_surface_flip_and_addr()
430 address->video_progressive.chroma_addr.high_part); in hubp401_program_surface_flip_and_addr()
438 address->video_progressive.luma_addr.high_part); in hubp401_program_surface_flip_and_addr()
458 address->grph_stereo.right_alpha_addr.high_part); in hubp401_program_surface_flip_and_addr()
466 address->grph_stereo.right_addr.high_part); in hubp401_program_surface_flip_and_addr()
474 address->grph_stereo.left_alpha_addr.high_part); in hubp401_program_surface_flip_and_addr()
482 address->grph_stereo.left_addr.high_part); in hubp401_program_surface_flip_and_addr()
499 address->rgbea.alpha_addr.high_part); in hubp401_program_surface_flip_and_addr()
507 address->rgbea.addr.high_part); in hubp401_program_surface_flip_and_addr()
/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
A Ddcn20_hubp.c617 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); in hubp2_cursor_set_attributes()
637 hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part; in hubp2_cursor_set_attributes()
678 DMDATA_ADDRESS_HIGH, attr->address.high_part); in hubp2_dmdata_set_attributes()
766 address->grph.meta_addr.high_part); in hubp2_program_surface_flip_and_addr()
775 address->grph.addr.high_part); in hubp2_program_surface_flip_and_addr()
812 address->video_progressive.chroma_addr.high_part); in hubp2_program_surface_flip_and_addr()
820 address->video_progressive.luma_addr.high_part); in hubp2_program_surface_flip_and_addr()
846 address->grph_stereo.right_meta_addr.high_part); in hubp2_program_surface_flip_and_addr()
856 address->grph_stereo.left_meta_addr.high_part); in hubp2_program_surface_flip_and_addr()
865 address->grph_stereo.right_addr.high_part); in hubp2_program_surface_flip_and_addr()
[all …]
/drivers/gpu/drm/amd/display/dc/inc/
A Dcompressor.h43 int32_t high_part; member
/drivers/gpu/drm/amd/display/dc/
A Ddc_hw_types.h48 int32_t high_part; member
53 int32_t high_part; member
A Ddc_dmub_srv.c1894 (uint16_t)address->grph.meta_addr.high_part; in dc_dmub_srv_fams2_passthrough_flip()
1898 (uint16_t)address->grph.addr.high_part; in dc_dmub_srv_fams2_passthrough_flip()
1910 (uint16_t)address->video_progressive.luma_meta_addr.high_part; in dc_dmub_srv_fams2_passthrough_flip()
1914 (uint16_t)address->video_progressive.chroma_meta_addr.high_part; in dc_dmub_srv_fams2_passthrough_flip()
1918 (uint16_t)address->video_progressive.luma_addr.high_part; in dc_dmub_srv_fams2_passthrough_flip()
1922 (uint16_t)address->video_progressive.chroma_addr.high_part; in dc_dmub_srv_fams2_passthrough_flip()
/drivers/gpu/drm/amd/display/dc/hubp/dcn32/
A Ddcn32_hubp.c125 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); in hubp32_cursor_set_attributes()
/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/
A Ddcn32_mmhubbub.c83 …(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.high_part); in mmhubbub32_warmup_mcif()
/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_mmhubbub.c83 …(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.high_part); in mmhubbub3_warmup_mcif()
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_ipp.c128 CURSOR_SURFACE_ADDRESS_HIGH, attributes->address.high_part); in dce_ipp_cursor_set_attributes()
A Ddce_mem_input.c821 address.high_part); in program_sec_addr()
835 address.high_part); in program_pri_addr()
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_plane.c351 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
871 address->grph.addr.high_part = upper_32_bits(addr); in amdgpu_dm_plane_fill_plane_buffer_attributes()
895 address->video_progressive.luma_addr.high_part = in amdgpu_dm_plane_fill_plane_buffer_attributes()
899 address->video_progressive.chroma_addr.high_part = in amdgpu_dm_plane_fill_plane_buffer_attributes()
1373 attributes.address.high_part = upper_32_bits(address); in amdgpu_dm_plane_handle_cursor_update()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A Ddcn316_clk_mgr.c420 clk_mgr_dcn316->smu_wm_set.mc_address.high_part); in dcn316_notify_wm_ranges()
440 smu_dpm_clks->mc_address.high_part); in dcn316_get_dpm_table_from_smu()
/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_mem_input_v.c67 temp = address.high_part & in program_pri_addr_c()
102 temp = address.high_part & in program_pri_addr_l()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c459 clk_mgr_vgh->smu_wm_set.mc_address.high_part); in vg_notify_wm_ranges()
655 smu_dpm_clks->mc_address.high_part); in vg_get_dpm_table_from_smu()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
A Ddcn315_clk_mgr.c455 clk_mgr_dcn315->smu_wm_set.mc_address.high_part); in dcn315_notify_wm_ranges()
475 smu_dpm_clks->mc_address.high_part); in dcn315_get_dpm_table_from_smu()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.c494 clk_mgr_dcn31->smu_wm_set.mc_address.high_part); in dcn31_notify_wm_ranges()
514 smu_dpm_clks->mc_address.high_part); in dcn31_get_dpm_table_from_smu()

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