| /drivers/soundwire/ |
| A D | bus.h | 168 int hstart; member
194 int hstart, int hstop, in sdw_fill_xport_params() argument
203 params->hstart = hstart; in sdw_fill_xport_params()
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| A D | generic_bandwidth_allocation.c | 62 t_data->hstart, in sdw_compute_slave_ports()
140 int sample_int, hstart = 0; in sdw_compute_master_ports() local
152 hstart = hstop - params->hwidth + 1; in sdw_compute_master_ports()
153 t_data.hstart = hstart; in sdw_compute_master_ports()
161 *port_bo, (*port_bo) >> 8, hstart, hstop, in sdw_compute_master_ports()
177 t_data.hstart = hstart; in sdw_compute_master_ports()
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| A D | amd_manager.c | 444 int port_bo, hstart, hstop, sample_int; in amd_sdw_compute_params() local
448 hstart = 1; in amd_sdw_compute_params()
451 t_data.hstart = hstart; in amd_sdw_compute_params()
460 p_rt->num, hstart, hstop, port_bo); in amd_sdw_compute_params()
463 port_bo, port_bo >> 8, hstart, hstop, in amd_sdw_compute_params()
470 t_data.hstart = hstart; in amd_sdw_compute_params()
577 dpn_hctrl |= FIELD_PREP(AMD_DPN_HCTRL_HSTART, params->hstart); in amd_sdw_transport_params()
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| A D | qcom.c | 154 u8 hstart; member
1022 if (pcfg->hstart != SWR_INVALID_PARAM in qcom_swrm_transport_params()
1025 value = (pcfg->hstop << 4) | pcfg->hstart; in qcom_swrm_transport_params()
1116 p_rt->transport_params.hstart = pcfg->hstart; in qcom_swrm_compute_params()
1359 u8 hstart[QCOM_SDW_MAX_PORTS]; in qcom_swrm_get_port_config() local
1426 memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); in qcom_swrm_get_port_config()
1427 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports); in qcom_swrm_get_port_config()
1450 ctrl->pconfig[i + 1].hstart = hstart[i]; in qcom_swrm_get_port_config()
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| A D | stream.c | 119 wbuf = FIELD_PREP(SDW_DPN_HCTRL_HSTART, t_params->hstart); in _sdw_program_slave_port_params()
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| A D | cadence_master.c | 1626 u32p_replace_bits(&dpn_hctrl, t_params->hstart, CDNS_DPN_HCTRL_HSTART); in cdns_transport_params()
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| /drivers/media/usb/gspca/ |
| A D | sn9c20x.c | 100 u8 hstart; member
1102 sd->hstart = 1; in ov9650_init_sensor()
1116 sd->hstart = 1; in ov9655_init_sensor()
1130 sd->hstart = 60; in soi968_init_sensor()
1143 sd->hstart = 3; in ov7660_init_sensor()
1157 sd->hstart = 0; in ov7670_init_sensor()
1175 sd->hstart = 2; in mt9v_init_sensor()
1234 sd->hstart = 0; in mt9m112_init_sensor()
1246 sd->hstart = 0; in mt9m111_init_sensor()
1278 sd->hstart = 1; in mt9m001_init_sensor()
[all …]
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| /drivers/gpu/drm/i915/display/ |
| A D | dvo_ns2501.c | 212 u16 hstart; /* horizontal start, registers C1/C2 */ member
239 .hstart = 144,
259 .hstart = 215,
278 .hstart = 276,
617 ns2501_writeb(dvo, NS2501_REGC1, conf->hstart & 0xff); in ns2501_mode_set()
618 ns2501_writeb(dvo, NS2501_REGC2, conf->hstart >> 8); in ns2501_mode_set()
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| /drivers/media/i2c/ |
| A D | ov7670.c | 194 int hstart; /* Start/stop values for the camera. Note */ member
729 .hstart = 158, /* These values from */
740 .hstart = 170, /* Empirically determined */
751 .hstart = 168, /* Empirically determined */
762 .hstart = 456, /* Empirically determined */
780 .hstart = 158, /* These values from */
915 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop, in ov7670_set_hw() argument
925 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff); in ov7670_set_hw()
934 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); in ov7670_set_hw()
1069 ret = ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart, in ov7670_apply_fmt()
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| A D | mt9v011.c | 272 unsigned vstart, hstart; in set_res() local
285 hstart = 20 + (640 - core->width) / 2; in set_res()
286 mt9v011_write(sd, R02_MT9V011_COLSTART, hstart); in set_res()
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| A D | mt9t112.c | 347 u16 hstart = (MAX_HEIGHT - height) / 2; in mt9t112_set_a_frame_size() local
358 mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart); in mt9t112_set_a_frame_size()
362 mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart); in mt9t112_set_a_frame_size()
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| /drivers/gpu/drm/msm/hdmi/ |
| A D | hdmi_bridge.c | 357 int hstart, hend, vstart, vend; in msm_hdmi_set_timings() local
360 hstart = mode->htotal - mode->hsync_start; in msm_hdmi_set_timings()
367 mode->htotal, mode->vtotal, hstart, hend, vstart, vend); in msm_hdmi_set_timings()
374 HDMI_ACTIVE_HSYNC_START(hstart) | in msm_hdmi_set_timings()
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| /drivers/gpu/drm/hisilicon/hibmc/dp/ |
| A D | dp_hw.c | 84 u32 hstart; in hibmc_dp_link_cfg() local
89 hstart = mode->htotal - mode->hsync_start; in hibmc_dp_link_cfg()
127 HIBMC_DP_CFG_STREAM_HSTART, hstart); in hibmc_dp_link_cfg()
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| /drivers/net/ethernet/marvell/octeontx2/af/ |
| A D | rvu_npc_fs.c | 484 #define NPC_SCAN_HDR(name, hlid, hlt, hstart, hlen) \ in npc_scan_ldata() argument
489 if ((hstart) >= hdr && \ in npc_scan_ldata()
490 ((hstart) + (hlen)) <= (hdr + nr_bytes)) { \ in npc_scan_ldata()
491 bit_offset = (hdr + nr_bytes - (hstart) - (hlen)) * 8; \ in npc_scan_ldata()
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| /drivers/media/usb/em28xx/ |
| A D | em28xx-video.c | 259 static void em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart, in em28xx_capture_area_set() argument
268 hstart, vstart, in em28xx_capture_area_set()
272 em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1); in em28xx_capture_area_set()
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