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Searched refs:hsync_start (Results 1 – 25 of 226) sorted by relevance

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/drivers/gpu/drm/panel/
A Dpanel-simple.c827 .hsync_start = 480 + 2,
851 .hsync_start = 800 + 0,
1094 .hsync_start = 800 + 40,
1118 .hsync_start = 800 + 40,
1627 .hsync_start = 480 + 5,
2020 .hsync_start = 480 + 8,
2050 .hsync_start = 480 + 2,
2194 .hsync_start = 640,
2387 .hsync_start = 480 + 5,
2541 .hsync_start = 480 + 2,
[all …]
A Dpanel-edp.c1017 .hsync_start = 1366 + 40,
1030 .hsync_start = 1366 + 48,
1085 .hsync_start = 1366 + 48,
1192 .hsync_start = 1920 + 48,
1324 .hsync_start = 1920 + 40,
1346 .hsync_start = 2160 + 48,
1373 .hsync_start = 1366 + 40,
1399 .hsync_start = 1536 + 12,
1442 .hsync_start = 1920 + 40,
1464 .hsync_start = 2560 + 48,
[all …]
A Dpanel-arm-versatile.c139 .hsync_start = 320 + 6,
162 .hsync_start = 640 + 24,
184 .hsync_start = 176 + 2,
207 .hsync_start = 240 + 10,
A Dpanel-tpo-tpg110.c107 .hsync_start = 800 + 40,
123 .hsync_start = 640 + 24,
139 .hsync_start = 480 + 2,
155 .hsync_start = 480 + 2,
171 .hsync_start = 400 + 20,
A Dpanel-ilitek-ili9322.c539 .hsync_start = 320 + 359,
552 .hsync_start = 360 + 35,
566 .hsync_start = 320 + 38,
580 .hsync_start = 640 + 252,
593 .hsync_start = 720 + 252,
607 .hsync_start = 640 + 3,
621 .hsync_start = 720 + 3,
A Dpanel-newvision-nv3052c.c829 .hsync_start = 640 + 96,
841 .hsync_start = 640 + 39,
856 .hsync_start = 640 + 34,
871 .hsync_start = 640 + 64,
A Dpanel-sitronix-st7703.c136 .hsync_start = 720 + 90,
315 .hsync_start = 720 + 40,
402 .hsync_start = 640 + 40,
486 .hsync_start = 720 + 45,
572 .hsync_start = 720 + 40,
654 .hsync_start = 640 + 40,
A Dpanel-novatek-nt35560.c63 .hsync_start = 480 + 15,
82 .hsync_start = 480 + 154,
105 .hsync_start = 480 + 15,
124 .hsync_start = 480 + 154,
A Dpanel-himax-hx8394.c183 .hsync_start = 720 + 40,
312 .hsync_start = 720 + 44,
459 .hsync_start = 720 + 12,
600 .hsync_start = 1080 + 32,
A Dpanel-newvision-nv3051d.c438 .hsync_start = 640 + 40,
450 .hsync_start = 640 + 40,
462 .hsync_start = 640 + 40,
477 .hsync_start = 640 + 40,
A Dpanel-leadtek-ltk050h3146w.c301 .hsync_start = 720 + 12,
382 .hsync_start = 720 + 42,
441 .hsync_start = 720 + 42,
/drivers/gpu/drm/msm/dp/
A Ddp_panel.c318 display_v_start += drm_mode->htotal - drm_mode->hsync_start; in msm_dp_panel_tpg_enable()
319 display_v_end -= (drm_mode->hsync_start - drm_mode->hdisplay); in msm_dp_panel_tpg_enable()
321 hsync_start_x = drm_mode->htotal - drm_mode->hsync_start; in msm_dp_panel_tpg_enable()
322 hsync_end_x = hsync_period - (drm_mode->hsync_start - in msm_dp_panel_tpg_enable()
328 (drm_mode->hsync_end - drm_mode->hsync_start); in msm_dp_panel_tpg_enable()
551 drm_mode->hsync_start - drm_mode->hdisplay, in msm_dp_panel_timing_cfg()
552 drm_mode->hsync_end - drm_mode->hsync_start); in msm_dp_panel_timing_cfg()
571 data |= (drm_mode->htotal - drm_mode->hsync_start); in msm_dp_panel_timing_cfg()
578 data |= drm_mode->hsync_end - drm_mode->hsync_start; in msm_dp_panel_timing_cfg()
631 drm_mode->hsync_start - drm_mode->hdisplay, in msm_dp_panel_init_panel_info()
[all …]
/drivers/gpu/drm/gud/
A Dgud_internal.h136 dst->hsync_start = cpu_to_le16(src->hsync_start); in gud_from_display_mode()
154 dst->hsync_start = le16_to_cpu(src->hsync_start); in gud_to_display_mode()
/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5_encoder.c73 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp5_vid_encoder_mode_set()
74 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp5_vid_encoder_mode_set()
87 display_v_start += mode->htotal - mode->hsync_start; in mdp5_vid_encoder_mode_set()
88 display_v_end -= mode->hsync_start - mode->hdisplay; in mdp5_vid_encoder_mode_set()
94 MDP5_INTF_HSYNC_CTL_PULSEW(mode->hsync_end - mode->hsync_start) | in mdp5_vid_encoder_mode_set()
/drivers/gpu/drm/
A Ddrm_modes.c457 mode->hsync_start = mode->hdisplay + hfp; in fill_analog_mode()
458 mode->hsync_end = mode->hsync_start + hslen; in fill_analog_mode()
762 drm_mode->hsync_start = drm_mode->hsync_end - in drm_cvt_mode()
764 drm_mode->hsync_start += CVT_H_GRANULARITY - in drm_cvt_mode()
765 drm_mode->hsync_start % CVT_H_GRANULARITY; in drm_cvt_mode()
1355 p->crtc_hsync_start = p->hsync_start; in drm_mode_set_crtcinfo()
1476 mode1->hsync_start == mode2->hsync_start && in drm_mode_match_timings()
1644 mode->hsync_start < mode->hdisplay || in drm_mode_validate_basic()
1645 mode->hsync_end < mode->hsync_start || in drm_mode_validate_basic()
2587 out->hsync_start = in->hsync_start; in drm_mode_convert_to_umode()
[all …]
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_encoders.c171 unsigned int hover = native_mode->hsync_start - native_mode->hdisplay; in amdgpu_panel_mode_fixup()
173 unsigned int hsync_width = native_mode->hsync_end - native_mode->hsync_start; in amdgpu_panel_mode_fixup()
183 adjusted_mode->hsync_start = native_mode->hdisplay + hover; in amdgpu_panel_mode_fixup()
184 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; in amdgpu_panel_mode_fixup()
/drivers/gpu/drm/msm/disp/mdp4/
A Dmdp4_dsi_encoder.c51 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_dsi_encoder_mode_set()
52 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dsi_encoder_mode_set()
60 MDP4_DSI_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) | in mdp4_dsi_encoder_mode_set()
A Dmdp4_dtv_encoder.c55 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_dtv_encoder_mode_set()
56 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dtv_encoder_mode_set()
64 MDP4_DTV_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) | in mdp4_dtv_encoder_mode_set()
/drivers/gpu/drm/i915/display/
A Dintel_vblank.c76 u32 pixel, vbl_start, hsync_start, htotal; in i915_get_vblank_counter() local
94 hsync_start = mode->crtc_hsync_start; in i915_get_vblank_counter()
101 vbl_start -= htotal - hsync_start; in i915_get_vblank_counter()
335 int vbl_start, vbl_end, hsync_start, htotal, vtotal; in i915_get_crtc_scanoutpos() local
349 hsync_start = mode->crtc_hsync_start; in i915_get_crtc_scanoutpos()
419 position = (position + htotal - hsync_start) % vtotal; in i915_get_crtc_scanoutpos()
/drivers/gpu/drm/tests/
A Ddrm_modes_test.c58 KUNIT_EXPECT_EQ(test, mode->hsync_start, 736); in drm_test_modes_analog_tv_ntsc_480i()
116 KUNIT_EXPECT_EQ(test, mode->hsync_start, 732); in drm_test_modes_analog_tv_pal_576i()
174 KUNIT_EXPECT_EQ(test, mode->hsync_start, 732); in drm_test_modes_analog_tv_mono_576i()
/drivers/gpu/drm/imx/dcss/
A Ddcss-ss.c124 u16 hsync_start, hsync_end; in dcss_ss_sync_set() local
136 hsync_start = vm->hfront_porch + vm->hback_porch + vm->hsync_len + in dcss_ss_sync_set()
141 ((u32)hsync_end << SYNC_END_POS) | hsync_start, in dcss_ss_sync_set()
/drivers/gpu/drm/radeon/
A Dradeon_encoders.c329 unsigned int hover = native_mode->hsync_start - native_mode->hdisplay; in radeon_panel_mode_fixup()
331 unsigned int hsync_width = native_mode->hsync_end - native_mode->hsync_start; in radeon_panel_mode_fixup()
343 adjusted_mode->hsync_start = native_mode->hdisplay + hover; in radeon_panel_mode_fixup()
344 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; in radeon_panel_mode_fixup()
A Dradeon_legacy_crtc.c60 int hsync_start; in radeon_legacy_rmx_mode_set() local
90 hsync_start = mode->crtc_hsync_start - 8; in radeon_legacy_rmx_mode_set()
92 fp_h_sync_strt_wid = ((hsync_start & 0x1fff) in radeon_legacy_rmx_mode_set()
581 int hsync_start; in radeon_set_crtc_timing() local
628 hsync_start = mode->crtc_hsync_start - 8; in radeon_set_crtc_timing()
630 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) in radeon_set_crtc_timing()
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_encoder_phys_vid.c51 || (mode->hsync_start < mode->hdisplay) in drm_mode_to_intf_timing_params()
54 || (mode->hsync_end < mode->hsync_start) in drm_mode_to_intf_timing_params()
58 mode->hsync_start, mode->hsync_end, in drm_mode_to_intf_timing_params()
80 timing->h_front_porch = mode->hsync_start - mode->hdisplay; in drm_mode_to_intf_timing_params()
83 timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start; in drm_mode_to_intf_timing_params()
285 mode.hsync_start >>= 1; in dpu_encoder_phys_vid_setup_timing_engine()
293 mode.hsync_start, mode.hsync_end, in dpu_encoder_phys_vid_setup_timing_engine()
/drivers/gpu/drm/bridge/adv7511/
A Dadv7533.c34 hsw = mode->hsync_end - mode->hsync_start; in adv7533_dsi_config_timing_gen()
35 hfp = mode->hsync_start - mode->hdisplay; in adv7533_dsi_config_timing_gen()

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