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Searched refs:htotal (Results 1 – 25 of 317) sorted by relevance

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/drivers/gpu/drm/panel/
A Dpanel-simple.c829 .htotal = 480 + 2 + 41 + 2,
853 .htotal = 800 + 0 + 255 + 0,
988 .htotal = 1366 + 20 + 70,
1229 .htotal = 1560,
1629 .htotal = 480 + 5 + 5 + 40,
1971 .htotal = 320 + 20 + 68,
1996 .htotal = 320 + 20 + 68,
2022 .htotal = 480 + 8 + 4 + 41,
2052 .htotal = 480 + 2 + 41 + 2,
2389 .htotal = 480 + 5 + 1 + 40,
[all …]
A Dpanel-edp.c1019 .htotal = 1366 + 40 + 40 + 32,
1032 .htotal = 1366 + 48 + 32 + 10,
1087 .htotal = 1366 + 48 + 32 + 20,
1235 .htotal = 2200,
1326 .htotal = 1920 + 40 + 40 + 80,
1348 .htotal = 2160 + 48 + 32 + 80,
1375 .htotal = 1366 + 40 + 32 + 62,
1401 .htotal = 1536 + 12 + 16 + 48,
1423 .htotal = 2048 + 150 + 5 + 5,
1444 .htotal = 1920 + 40 + 40 + 80,
[all …]
A Dpanel-arm-versatile.c141 .htotal = 320 + 6 + 6 + 6,
164 .htotal = 640 + 24 + 96 + 24,
186 .htotal = 176 + 2 + 3 + 3,
209 .htotal = 240 + 10 + 10 + 20,
/drivers/gpu/drm/msm/disp/mdp4/
A Dmdp4_dsi_encoder.c51 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_dsi_encoder_mode_set()
52 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dsi_encoder_mode_set()
54 vsync_period = mode->vtotal * mode->htotal; in mdp4_dsi_encoder_mode_set()
55 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp4_dsi_encoder_mode_set()
56 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dsi_hsync_skew; in mdp4_dsi_encoder_mode_set()
57 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dsi_hsync_s… in mdp4_dsi_encoder_mode_set()
61 MDP4_DSI_HSYNC_CTRL_PERIOD(mode->htotal)); in mdp4_dsi_encoder_mode_set()
A Dmdp4_dtv_encoder.c55 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_dtv_encoder_mode_set()
56 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dtv_encoder_mode_set()
58 vsync_period = mode->vtotal * mode->htotal; in mdp4_dtv_encoder_mode_set()
59 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp4_dtv_encoder_mode_set()
60 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; in mdp4_dtv_encoder_mode_set()
61 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_s… in mdp4_dtv_encoder_mode_set()
65 MDP4_DTV_HSYNC_CTRL_PERIOD(mode->htotal)); in mdp4_dtv_encoder_mode_set()
A Dmdp4_lcdc_encoder.c228 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_lcdc_encoder_mode_set()
229 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_lcdc_encoder_mode_set()
231 vsync_period = mode->vtotal * mode->htotal; in mdp4_lcdc_encoder_mode_set()
232 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp4_lcdc_encoder_mode_set()
233 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + lcdc_hsync_skew; in mdp4_lcdc_encoder_mode_set()
234 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + lcdc_hsync_… in mdp4_lcdc_encoder_mode_set()
238 MDP4_LCDC_HSYNC_CTRL_PERIOD(mode->htotal)); in mdp4_lcdc_encoder_mode_set()
/drivers/gpu/drm/i915/display/
A Dintel_vblank.c93 htotal = mode->crtc_htotal; in i915_get_vblank_counter()
98 vbl_start *= htotal; in i915_get_vblank_counter()
101 vbl_start -= htotal - hsync_start; in i915_get_vblank_counter()
139 u32 htotal = mode->crtc_htotal; in intel_crtc_scanlines_since_frame_timestamp() local
169 clock), 1000 * htotal); in intel_crtc_scanlines_since_frame_timestamp()
348 htotal = mode->crtc_htotal; in i915_get_crtc_scanoutpos()
395 vbl_start *= htotal; in i915_get_crtc_scanoutpos()
396 vbl_end *= htotal; in i915_get_crtc_scanoutpos()
397 vtotal *= htotal; in i915_get_crtc_scanoutpos()
446 *vpos = position / htotal; in i915_get_crtc_scanoutpos()
[all …]
A Dintel_tv.c323 u16 hblank_start, hblank_end, htotal; member
397 .hblank_start = 836, .htotal = 857,
439 .hblank_start = 836, .htotal = 857,
482 .hblank_start = 836, .htotal = 857,
525 .hblank_start = 836, .htotal = 857,
568 .hblank_start = 844, .htotal = 863,
613 .hblank_start = 844, .htotal = 863,
1011 tv_mode->htotal - tv_mode->hblank_start; in intel_tv_mode_to_mode()
1014 mode->htotal = tv_mode->htotal + 1; in intel_tv_mode_to_mode()
1070 mode->htotal = new_htotal; in intel_tv_scale_mode_horiz()
[all …]
/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5_encoder.c73 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp5_vid_encoder_mode_set()
74 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp5_vid_encoder_mode_set()
76 vsync_period = mode->vtotal * mode->htotal; in mdp5_vid_encoder_mode_set()
77 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp5_vid_encoder_mode_set()
78 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; in mdp5_vid_encoder_mode_set()
79 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_s… in mdp5_vid_encoder_mode_set()
87 display_v_start += mode->htotal - mode->hsync_start; in mdp5_vid_encoder_mode_set()
95 MDP5_INTF_HSYNC_CTL_PERIOD(mode->htotal)); in mdp5_vid_encoder_mode_set()
/drivers/media/i2c/
A Dths8200.c61 static inline unsigned htotal(const struct v4l2_bt_timings *t) in htotal() function
252 ths8200_write(sd, THS8200_DTG1_SPEC_G_LSB, (htotal(bt)/2) & 0xff); in ths8200_setup()
254 ((htotal(bt)/2) >> 8) & 0x0f); in ths8200_setup()
257 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_MSB, htotal(bt) >> 8); in ths8200_setup()
258 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_LSB, htotal(bt) & 0xff); in ths8200_setup()
308 (htotal(bt) >> 8) & 0x1f); in ths8200_setup()
309 ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt)); in ths8200_setup()
356 "vertical: sync %d\n", __func__, htotal(bt), vtotal(bt), in ths8200_setup()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_rq_dlg_calc_20.c798 unsigned int htotal = dst->htotal; in dml20_rq_dlg_get_dlg_params() local
982 line_time_in_us = (htotal / pclk_freq_in_mhz); in dml20_rq_dlg_get_dlg_params()
1106 if (htotal <= 75) { in dml20_rq_dlg_get_dlg_params()
1390 (unsigned int) (dst_y_per_row_vblank * (double) htotal in dml20_rq_dlg_get_dlg_params()
1396 * (double) htotal * ref_freq_to_pix_freq in dml20_rq_dlg_get_dlg_params()
1403 (unsigned int) (dst_y_per_row_vblank * (double) htotal in dml20_rq_dlg_get_dlg_params()
1417 * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; in dml20_rq_dlg_get_dlg_params()
1444 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq in dml20_rq_dlg_get_dlg_params()
1449 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq in dml20_rq_dlg_get_dlg_params()
1457 * (double) htotal * ref_freq_to_pix_freq in dml20_rq_dlg_get_dlg_params()
[all …]
A Ddisplay_rq_dlg_calc_20v2.c798 unsigned int htotal = dst->htotal; in dml20v2_rq_dlg_get_dlg_params() local
983 line_time_in_us = (htotal / pclk_freq_in_mhz); in dml20v2_rq_dlg_get_dlg_params()
1107 if (htotal <= 75) { in dml20v2_rq_dlg_get_dlg_params()
1391 (unsigned int) (dst_y_per_row_vblank * (double) htotal in dml20v2_rq_dlg_get_dlg_params()
1397 * (double) htotal * ref_freq_to_pix_freq in dml20v2_rq_dlg_get_dlg_params()
1404 (unsigned int) (dst_y_per_row_vblank * (double) htotal in dml20v2_rq_dlg_get_dlg_params()
1418 * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; in dml20v2_rq_dlg_get_dlg_params()
1445 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq in dml20v2_rq_dlg_get_dlg_params()
1450 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq in dml20v2_rq_dlg_get_dlg_params()
1458 * (double) htotal * ref_freq_to_pix_freq in dml20v2_rq_dlg_get_dlg_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_rq_dlg_calc_21.c844 unsigned int htotal = dst->htotal; in dml_rq_dlg_get_dlg_params() local
1034 line_time_in_us = (htotal / pclk_freq_in_mhz); in dml_rq_dlg_get_dlg_params()
1156 if (htotal <= 75) { in dml_rq_dlg_get_dlg_params()
1465 (unsigned int) (dst_y_per_row_vblank * (double) htotal in dml_rq_dlg_get_dlg_params()
1475 * (double) htotal * ref_freq_to_pix_freq in dml_rq_dlg_get_dlg_params()
1487 (unsigned int) (dst_y_per_row_vblank * (double) htotal in dml_rq_dlg_get_dlg_params()
1503 * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; in dml_rq_dlg_get_dlg_params()
1552 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq in dml_rq_dlg_get_dlg_params()
1557 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq in dml_rq_dlg_get_dlg_params()
1565 * (double) htotal * ref_freq_to_pix_freq in dml_rq_dlg_get_dlg_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calc_auto.c785 v->v_update_offset[k][j] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0); in mode_support_and_system_configuration()
802 …htotal[k] / v->pixel_clock[k]) - (v->time_calc + v->time_setup) / (v->htotal[k] / v->pixel_clock[k… in mode_support_and_system_configuration()
810 v->htotal[k] / v->pixel_clock[k] / 4.0); in mode_support_and_system_configuration()
812 v->time_for_meta_pte_without_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0; in mode_support_and_system_configuration()
818 v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip, in mode_support_and_system_configuration()
822 v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip, in mode_support_and_system_configuration()
850 v->time_for_meta_pte_with_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0; in mode_support_and_system_configuration()
1393 v->v_blank_time = (v->vtotal[k] - v->vactive[k]) * v->htotal[k] / v->pixel_clock[k]; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1653 v->v_update_offset_pix[k] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1668 …htotal[k] / v->pixel_clock[k]) - (v->t_calc + v->t_setup) / (v->htotal[k] / v->pixel_clock[k]) - (… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
[all …]
/drivers/video/fbdev/core/
A Dfbmon.c724 int vtotal, htotal; in fb_get_monitor_limits() local
747 hscan = (pixclock + htotal / 2) / htotal; in fb_get_monitor_limits()
1026 u32 htotal; member
1158 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_vfreq()
1169 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_hfreq()
1177 timings->hfreq = timings->dclk/timings->htotal; in fb_timings_dclk()
1298 var->hsync_len = (timings->htotal * 8)/100; in fb_get_mode()
1316 unsigned int htotal, vtotal, total; in fb_videomode_from_videomode() local
1349 total = htotal * vtotal; in fb_videomode_from_videomode()
1438 u32 hfreq, vfreq, htotal, vtotal, pixclock; in fb_validate_mode() local
[all …]
A Dfbcvt.c44 u32 htotal; member
132 hsync = (FB_CVT_CELLSIZE * cvt->htotal)/100; in fb_cvt_hsync()
177 pixclock = (cvt->f_refresh * cvt->vtotal * cvt->htotal)/1000; in fb_cvt_pixclock()
179 pixclock = (cvt->htotal * 1000000)/cvt->hperiod; in fb_cvt_pixclock()
354 cvt.htotal = cvt.active_pixels + cvt.hblank; in fb_find_mode_cvt()
357 cvt.hfreq = cvt.pixclock/cvt.htotal; in fb_find_mode_cvt()
/drivers/gpu/drm/mgag200/
A Dmgag200_mode.c193 unsigned int hdispend, hsyncstr, hsyncend, htotal, hblkstr, hblkend; in mgag200_set_mode_regs() local
201 htotal = mode->crtc_htotal / 8 - 1; in mgag200_set_mode_regs()
203 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) in mgag200_set_mode_regs()
204 htotal++; in mgag200_set_mode_regs()
206 hblkend = htotal; in mgag200_set_mode_regs()
229 crtcext1 = (((htotal - 4) & 0x100) >> 8) | in mgag200_set_mode_regs()
244 WREG_CRT(0x00, htotal - 4); in mgag200_set_mode_regs()
572 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { in mgag200_crtc_helper_mode_valid()
745 if (!mode->htotal || !mode->vtotal || !mode->clock) in mgag200_calculate_mode_bandwidth()
749 total_area = mode->htotal * mode->vtotal; in mgag200_calculate_mode_bandwidth()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_rq_dlg_calc_30.c910 unsigned int htotal = dst->htotal; in dml_rq_dlg_get_dlg_params() local
1095 line_time_in_us = (htotal / pclk_freq_in_mhz); in dml_rq_dlg_get_dlg_params()
1260 if (htotal <= 75) { in dml_rq_dlg_get_dlg_params()
1567 (unsigned int)(dst_y_per_row_vblank * (double)htotal in dml_rq_dlg_get_dlg_params()
1573 * (double)htotal * ref_freq_to_pix_freq in dml_rq_dlg_get_dlg_params()
1580 (unsigned int)(dst_y_per_row_vblank * (double)htotal in dml_rq_dlg_get_dlg_params()
1594 * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; in dml_rq_dlg_get_dlg_params()
1641 / (double)vratio_l * (double)htotal * ref_freq_to_pix_freq in dml_rq_dlg_get_dlg_params()
1646 / (double)vratio_l * (double)htotal * ref_freq_to_pix_freq in dml_rq_dlg_get_dlg_params()
1654 * (double)htotal * ref_freq_to_pix_freq in dml_rq_dlg_get_dlg_params()
[all …]
/drivers/gpu/drm/gud/
A Dgud_internal.h138 dst->htotal = cpu_to_le16(src->htotal); in gud_from_display_mode()
156 dst->htotal = le16_to_cpu(src->htotal); in gud_to_display_mode()
/drivers/gpu/drm/hisilicon/hibmc/dp/
A Ddp_hw.c60 htotal_int = mode->htotal * 9947 / 10000; in hibmc_dp_set_sst()
63 hblank_int = mode->htotal - mode->hdisplay - mode->hdisplay * 53 / 10000; in hibmc_dp_set_sst()
88 timing_delay = mode->htotal - mode->hsync_start; in hibmc_dp_link_cfg()
89 hstart = mode->htotal - mode->hsync_start; in hibmc_dp_link_cfg()
93 HIBMC_DP_CFG_TIMING_GEN0_HBLANK, mode->htotal - mode->hdisplay); in hibmc_dp_link_cfg()
108 HIBMC_DP_CFG_STREAM_HBLANK, mode->htotal - mode->hdisplay); in hibmc_dp_link_cfg()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_rq_dlg_calc_31.c873 unsigned int htotal = dst->htotal; in dml_rq_dlg_get_dlg_params() local
976 …disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_po… in dml_rq_dlg_get_dlg_params()
1028 …if (vstartup_start / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= v… in dml_rq_dlg_get_dlg_params()
1033 …if (vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_… in dml_rq_dlg_get_dlg_params()
1091 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); in dml_rq_dlg_get_dlg_params()
1105 if (htotal <= 75) { in dml_rq_dlg_get_dlg_params()
1431 …disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_fre… in dml_rq_dlg_get_dlg_params()
1432 …disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_fr… in dml_rq_dlg_get_dlg_params()
1435 …disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_fre… in dml_rq_dlg_get_dlg_params()
1436 …disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_fr… in dml_rq_dlg_get_dlg_params()
[all …]
/drivers/video/fbdev/matrox/
A Dmatroxfb_maven.c226 unsigned int htotal, unsigned int vtotal, in matroxfb_PLL_mavenclock() argument
239 scrlen = htotal * (vtotal - 1); in matroxfb_PLL_mavenclock()
240 fwant = htotal * vtotal; in matroxfb_PLL_mavenclock()
244 fwant, fxtal, htotal, vtotal, fmax); in matroxfb_PLL_mavenclock()
277 if (ln > htotal) in matroxfb_PLL_mavenclock()
299 unsigned int htotal, unsigned int vtotal, in matroxfb_mavenclock() argument
748 m->htotal = h - 2; in maven_find_exact_clocks()
801 m->regs[0xA0] = m->htotal; in maven_compute_timming()
802 m->regs[0xA1] = m->htotal >> 8; in maven_compute_timming()
873 if (ib >= m->htotal + 2) { in maven_compute_timming()
[all …]
/drivers/gpu/drm/
A Ddrm_modes.c334 unsigned int htotal, vtotal; in fill_analog_mode() local
368 htotal = result; in fill_analog_mode()
381 hblk = htotal - hactive; in fill_analog_mode()
452 if (htotal != (hactive + hfp + hslen + hbp)) in fill_analog_mode()
459 mode->htotal = mode->hsync_end + hbp; in fill_analog_mode()
996 drm_mode->htotal = total_pixels; in drm_gtf_mode_complex()
1357 p->crtc_htotal = p->htotal; in drm_mode_set_crtcinfo()
1478 mode1->htotal == mode2->htotal && in drm_mode_match_timings()
1646 mode->htotal < mode->hsync_end) in drm_mode_validate_basic()
2589 out->htotal = in->htotal; in drm_mode_convert_to_umode()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/
A Ddml1_display_rq_dlg_calc.c1009 unsigned int htotal = e2e_pipe_param->pipe.dest.htotal; in dml1_rq_dlg_get_dlg_params() local
1223 line_time_in_us = (htotal / pclk_freq_in_mhz); in dml1_rq_dlg_get_dlg_params()
1289 if (dst_x_after_scaler >= htotal) { in dml1_rq_dlg_get_dlg_params()
1290 dst_x_after_scaler = dst_x_after_scaler - htotal; in dml1_rq_dlg_get_dlg_params()
1483 if (htotal <= 75) { in dml1_rq_dlg_get_dlg_params()
1530 (unsigned int) (dst_y_per_row_vblank * (double) htotal in dml1_rq_dlg_get_dlg_params()
1535 (unsigned int) (dst_y_per_row_vblank * (double) htotal in dml1_rq_dlg_get_dlg_params()
1540 (unsigned int) (dst_y_per_row_vblank * (double) htotal in dml1_rq_dlg_get_dlg_params()
1573 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq in dml1_rq_dlg_get_dlg_params()
1579 / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq in dml1_rq_dlg_get_dlg_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddisplay_rq_dlg_calc_314.c958 unsigned int htotal = dst->htotal; in dml_rq_dlg_get_dlg_params() local
1061 …disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_po… in dml_rq_dlg_get_dlg_params()
1115 …if (vstartup_start / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= v… in dml_rq_dlg_get_dlg_params()
1120 …if (vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_… in dml_rq_dlg_get_dlg_params()
1179 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); in dml_rq_dlg_get_dlg_params()
1193 if (htotal <= 75) { in dml_rq_dlg_get_dlg_params()
1519 …disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_fre… in dml_rq_dlg_get_dlg_params()
1520 …disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_fr… in dml_rq_dlg_get_dlg_params()
1523 …disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_fre… in dml_rq_dlg_get_dlg_params()
1524 …disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_fr… in dml_rq_dlg_get_dlg_params()
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