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Searched refs:hw_ctl (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_encoder_phys_wb.c232 (phys_enc->hw_ctl && in dpu_encoder_phys_wb_setup_ctl()
259 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_wb_setup_ctl()
260 } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) { in dpu_encoder_phys_wb_setup_ctl()
267 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_wb_setup_ctl()
289 hw_ctl = phys_enc->hw_ctl; in _dpu_encoder_phys_wb_update_flush()
295 if (!hw_ctl) { in _dpu_encoder_phys_wb_update_flush()
301 hw_ctl->ops.update_pending_flush_wb(hw_ctl, hw_wb->idx); in _dpu_encoder_phys_wb_update_flush()
305 hw_ctl->ops.update_pending_flush_merge_3d(hw_ctl, in _dpu_encoder_phys_wb_update_flush()
309 hw_ctl->ops.update_pending_flush_cdm(hw_ctl, hw_cdm->idx); in _dpu_encoder_phys_wb_update_flush()
312 pending_flush = hw_ctl->ops.get_pending_flush(hw_ctl); in _dpu_encoder_phys_wb_update_flush()
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A Ddpu_encoder_phys_vid.c317 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_vid_setup_timing_engine()
336 struct dpu_hw_ctl *hw_ctl; in dpu_encoder_phys_vid_vblank_irq() local
340 hw_ctl = phys_enc->hw_ctl; in dpu_encoder_phys_vid_vblank_irq()
355 flush_register = hw_ctl->ops.get_flush_register(hw_ctl); in dpu_encoder_phys_vid_vblank_irq()
357 if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl))) in dpu_encoder_phys_vid_vblank_irq()
451 ctl = phys_enc->hw_ctl; in dpu_encoder_phys_vid_enable()
533 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl; in dpu_encoder_phys_vid_wait_for_commit_done() local
536 if (!hw_ctl) in dpu_encoder_phys_vid_wait_for_commit_done()
540 (hw_ctl->ops.get_flush_register(hw_ctl) == 0), in dpu_encoder_phys_vid_wait_for_commit_done()
543 DPU_ERROR("vblank timeout: %x\n", hw_ctl->ops.get_flush_register(hw_ctl)); in dpu_encoder_phys_vid_wait_for_commit_done()
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A Ddpu_encoder.c1214 drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); in dpu_encoder_virt_atomic_mode_set()
1252 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[0]); in dpu_encoder_virt_atomic_mode_set()
1254 phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL; in dpu_encoder_virt_atomic_mode_set()
1255 if (!phys->hw_ctl) { in dpu_encoder_virt_atomic_mode_set()
1635 ctl = phys->hw_ctl; in _dpu_encoder_trigger_flush()
1708 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_trigger_start()
1750 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_hw_reset()
1795 ctl = phys->hw_ctl; in _dpu_encoder_kickoff_phys()
1848 ctl = phys->hw_ctl; in dpu_encoder_trigger_kickoff_pending()
2358 hw_ctl = phys_enc->hw_ctl; in dpu_encoder_helper_phys_setup_cwb()
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A Ddpu_encoder_phys_cmd.c58 ctl = phys_enc->hw_ctl; in _dpu_encoder_phys_cmd_update_intf_cfg()
154 phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; in dpu_encoder_phys_cmd_atomic_mode_set()
199 phys_enc->hw_ctl->idx - CTL_0, in _dpu_encoder_phys_cmd_handle_ppdone_timeout()
423 if (!phys_enc->hw_pp || !phys_enc->hw_ctl->ops.setup_intf_cfg) { in _dpu_encoder_phys_cmd_pingpong_config()
460 ctl = phys_enc->hw_ctl; in dpu_encoder_phys_cmd_enable_helper()
568 ctl = phys_enc->hw_ctl; in dpu_encoder_phys_cmd_disable()
684 if (phys_enc->hw_ctl->ops.is_started(phys_enc->hw_ctl)) in dpu_encoder_phys_cmd_wait_for_commit_done()
A Ddpu_encoder_phys.h180 struct dpu_hw_ctl *hw_ctl; member
A Ddpu_crtc.c1372 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_CRTC]; in dpu_crtc_assign_resources() local
1404 DPU_HW_BLK_CTL, hw_ctl, in dpu_crtc_assign_resources()
1405 ARRAY_SIZE(hw_ctl)); in dpu_crtc_assign_resources()
1419 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); in dpu_crtc_assign_resources()

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