Home
last modified time | relevance | path

Searched refs:hw_pp (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_encoder_phys_cmd.c94 if (!phys_enc->hw_pp) in dpu_encoder_phys_cmd_pp_tx_done_irq()
175 if (!phys_enc->hw_pp) in _dpu_encoder_phys_cmd_handle_ppdone_timeout()
360 phys_enc->hw_pp ? phys_enc->hw_pp->idx - PINGPONG_0 : -1); in dpu_encoder_phys_cmd_tearcheck_config()
414 phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, &tc_cfg); in dpu_encoder_phys_cmd_tearcheck_config()
495 if (!phys_enc->hw_pp || !phys_enc->hw_pp->ops.connect_external_te) in _dpu_encoder_phys_cmd_connect_te()
499 phys_enc->hw_pp->ops.connect_external_te(phys_enc->hw_pp, enable); in _dpu_encoder_phys_cmd_connect_te()
525 hw_pp = phys_enc->hw_pp; in dpu_encoder_phys_cmd_get_line_count()
526 if (!hw_pp || !hw_pp->ops.get_line_count) in dpu_encoder_phys_cmd_get_line_count()
528 return hw_pp->ops.get_line_count(hw_pp); in dpu_encoder_phys_cmd_get_line_count()
560 phys_enc->hw_pp->ops.disable_tearcheck(phys_enc->hw_pp); in dpu_encoder_phys_cmd_disable()
[all …]
A Ddpu_encoder.c402 hw_pp->ops.setup_dither(hw_pp, NULL); in _dpu_encoder_setup_dither()
409 hw_pp->ops.setup_dither(hw_pp, &dither_cfg); in _dpu_encoder_setup_dither()
1194 hw_pp, ARRAY_SIZE(hw_pp)); in dpu_encoder_virt_atomic_mode_set()
1243 phys->hw_pp = dpu_enc->hw_pp[i]; in dpu_encoder_virt_atomic_mode_set()
1996 hw_pp->ops.setup_dsc(hw_pp); in dpu_encoder_dsc_pipe_cfg()
2002 hw_pp->ops.enable_dsc(hw_pp); in dpu_encoder_dsc_pipe_cfg()
2024 hw_pp[i] = dpu_enc->hw_pp[i]; in dpu_encoder_prep_dsc()
2221 hw_pp->ops.disable_dsc(hw_pp); in dpu_encoder_dsc_pipe_clr()
2240 hw_pp[i] = dpu_enc->hw_pp[i]; in dpu_encoder_unprep_dsc()
2331 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) in dpu_encoder_helper_phys_cleanup()
[all …]
A Ddpu_encoder_phys_wb.c235 struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp; in dpu_encoder_phys_wb_setup_ctl() local
244 if (mode_3d && hw_pp && hw_pp->merge_3d) in dpu_encoder_phys_wb_setup_ctl()
245 intf_cfg.merge_3d = hw_pp->merge_3d->idx; in dpu_encoder_phys_wb_setup_ctl()
250 if (phys_enc->hw_pp->merge_3d && phys_enc->hw_pp->merge_3d->ops.setup_3d_mode) in dpu_encoder_phys_wb_setup_ctl()
251 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, in dpu_encoder_phys_wb_setup_ctl()
255 if (hw_pp && phys_enc->hw_wb->ops.bind_pingpong_blk) in dpu_encoder_phys_wb_setup_ctl()
257 phys_enc->hw_pp->idx); in dpu_encoder_phys_wb_setup_ctl()
279 struct dpu_hw_pingpong *hw_pp; in _dpu_encoder_phys_wb_update_flush() local
288 hw_pp = phys_enc->hw_pp; in _dpu_encoder_phys_wb_update_flush()
304 hw_pp && hw_pp->merge_3d) in _dpu_encoder_phys_wb_update_flush()
[all …]
A Ddpu_encoder_phys_vid.c311 if (intf_cfg.mode_3d && phys_enc->hw_pp->merge_3d) in dpu_encoder_phys_vid_setup_timing_engine()
312 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; in dpu_encoder_phys_vid_setup_timing_engine()
323 phys_enc->hw_pp->idx); in dpu_encoder_phys_vid_setup_timing_engine()
325 if (phys_enc->hw_pp->merge_3d) in dpu_encoder_phys_vid_setup_timing_engine()
326 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); in dpu_encoder_phys_vid_setup_timing_engine()
478 phys_enc->hw_pp->merge_3d) in dpu_encoder_phys_vid_enable()
479 ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx); in dpu_encoder_phys_vid_enable()
A Ddpu_encoder_phys.h181 struct dpu_hw_pingpong *hw_pp; member

Completed in 20 milliseconds