Searched refs:i0 (Results 1 – 9 of 9) sorted by relevance
| /drivers/gpu/drm/etnaviv/ |
| A D | state.xml.h | 75 #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) argument
195 #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) argument
201 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) argument
203 #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) argument
213 #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0)) argument
225 #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0)) argument
331 #define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0)) argument
437 #define VIVS_GL_GS_UNK038A0(i0) (0x000038a0 + 0x4*(i0)) argument
441 #define VIVS_GL_HALTI5_UNK038C0(i0) (0x000038c0 + 0x4*(i0)) argument
512 #define VIVS_NFE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) argument
[all …]
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| A D | state_hi.xml.h | 342 #define VIVS_MMUv2_EXCEPTION_ADDR(i0) (0x00000190 + 0x4*(i0)) argument
354 #define VIVS_MMUv2_AXI_POLICY(i0) (0x000001c0 + 0x4*(i0)) argument
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| /drivers/char/hw_random/ |
| A D | n2-asm.S | 31 mov %i0, %o0
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| /drivers/soc/qcom/ |
| A D | ocmem.c | 95 #define OCMEM_REG_PSGSC_CTL(i0) (0x0000003c + 0x1*(i0)) argument
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| /drivers/gpu/drm/nouveau/include/nvif/ |
| A D | push.h | 101 #define PUSH_DATA_(X,p,m,i0,i1,d,s,f,a...) PUSH_DATA__((p), (d), "-> "#m f, ##a) argument
118 PUSH_DATA_(X, _pp, X##m, i0, i1, *_dd++, 1, "+0x%x", 0); \
120 PUSH_DATA_(X, _pp, X##m, i0, i1, *_dd++, 1, "+0x%x", _i); \
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| /drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/ |
| A D | g98.fuc0s | 109 // set interrupt dispatch - route timer, fifo, ctxswitch to i0, others to host
124 // enable i0 delivery
133 // i0 handler
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| /drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/ |
| A D | com.fuc | 140 // setup i0 handler and route fifo and ctxswitch to it
164 // i0 handler
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| /drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/ |
| A D | gpc.fuc | 137 // setup i0 handler, and route all interrupts to it
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| A D | hub.fuc | 83 // setup i0 handler, and route all interrupts to it
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