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/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.h177 SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \
195 SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \
196 SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \
197 SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \
198 SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \
199 SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \
204 SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
205 SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \
206 SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \
207 SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.h226 SRI_ARR(DC_ABM1_ACE_THRES_12, ABM, id), NBIO_SR_ARR(BIOS_SCRATCH_2, id)
235 SR_ARR(DCCG_AUDIO_DTO_SOURCE, id), SR_ARR(DCCG_AUDIO_DTO0_MODULE, id), \
236 SR_ARR(DCCG_AUDIO_DTO0_PHASE, id), SR_ARR(DCCG_AUDIO_DTO1_MODULE, id), \
256 SRI_ARR(AFMT_60958_2, AFMT, id), SRI_ARR(AFMT_MEM_PWR, AFMT, id)
261 SRI_ARR(APG_MEM_PWR, APG, id), SRI_ARR(APG_DBG_GEN_CONTROL, APG, id)
317 AUX_REG_LIST_RI(id), SRI_ARR(AUX_DPHY_TX_CONTROL, DP_AUX, id)
320 #define HPD_REG_LIST_RI(id) SRI_ARR(DC_HPD_CONTROL, HPD, id) argument
343 SR_ARR(DIO_LINKE_CNTL, id), SR_ARR(DIO_LINKF_CNTL, id)
553 #define OPP_REG_LIST_DCN10_RI(id) OPP_REG_LIST_DCN_RI(id) argument
559 SRI_ARR(DPG_RAMP_CONTROL, DPG, id), SRI_ARR(DPG_STATUS, DPG, id)
[all …]
/drivers/i2c/busses/
A Di2c-cadence.c549 id->curr_recv_count = id->recv_count; in cdns_i2c_master_isr()
666 if (id->recv_count <= id->fifo_depth && !id->bus_hold_flag) in cdns_i2c_mrecv_atomic()
726 id->p_recv_buf = id->p_msg->buf; in cdns_i2c_mrecv()
727 id->recv_count = id->p_msg->len; in cdns_i2c_mrecv()
741 id->curr_recv_count = id->recv_count; in cdns_i2c_mrecv()
747 if (id->recv_count > id->fifo_depth) in cdns_i2c_mrecv()
771 if (!id->bus_hold_flag && id->recv_count <= id->fifo_depth) { in cdns_i2c_mrecv()
848 id->p_send_buf = id->p_msg->buf; in cdns_i2c_msend()
849 id->send_count = id->p_msg->len; in cdns_i2c_msend()
860 if (id->send_count > id->fifo_depth) in cdns_i2c_msend()
[all …]
A Di2c-sh7760.c248 OUT32(id, I2CMAR, (id->msg->addr << 1) | 1); in sh7760_i2c_mrecv()
274 OUT32(id, I2CMAR, (id->msg->addr << 1) | 0); in sh7760_i2c_msend()
286 OUT32(id, I2CRXTX, *(id->msg->buf)); in sh7760_i2c_msend()
446 id = kzalloc(sizeof(*id), GFP_KERNEL); in sh7760_i2c_probe()
447 if (!id) { in sh7760_i2c_probe()
478 id->adap.nr = pdev->id; in sh7760_i2c_probe()
482 id->adap.algo_data = id; in sh7760_i2c_probe()
484 snprintf(id->adap.name, sizeof(id->adap.name), in sh7760_i2c_probe()
526 free_irq(id->irq, id); in sh7760_i2c_probe()
533 kfree(id); in sh7760_i2c_probe()
[all …]
/drivers/staging/media/ipu7/
A Dipu7-isys-csi-phy.c226 u32 id, lanes, phy_mode; in ipu7_isys_csi_ctrl_cfg() local
229 id = csi2->port; in ipu7_isys_csi_ctrl_cfg()
233 id, lanes, phy_mode); in ipu7_isys_csi_ctrl_cfg()
274 id, vc, dt); in __dids_config()
368 id, i, dwc_phy_read(isys, id, reg)); in ipu7_isys_phy_ready()
382 if (id) { in ipu7_isys_phy_ready()
511 id == PORT_B || id == PORT_C) { in ipu7_isys_dphy_config()
553 if (!is_ipu7(isys->adev->isp->hw_ver) || id == PORT_B || id == PORT_C) in ipu7_isys_dphy_config()
787 dwc_phy_write_mask(isys, id, in ipu7_isys_cphy_config()
947 isys->csi2[id].phy_mode); in ipu7_isys_phy_config()
[all …]
/drivers/clk/at91/
A Dsam9x60.c86 u8 id; member
102 u8 id; member
104 { .n = "pioA_clk", .id = 2, },
105 { .n = "pioB_clk", .id = 3, },
106 { .n = "pioC_clk", .id = 4, },
107 { .n = "flex0_clk", .id = 5, },
108 { .n = "flex1_clk", .id = 6, },
109 { .n = "flex2_clk", .id = 7, },
110 { .n = "flex3_clk", .id = 8, },
157 u8 id; member
[all …]
A Dsama5d4.c43 u8 id; member
61 u8 id; member
63 { .n = "pioD_clk", .id = 5 },
66 { .n = "icm_clk", .id = 9 },
67 { .n = "aes_clk", .id = 12 },
68 { .n = "tdes_clk", .id = 14 },
69 { .n = "sha_clk", .id = 15 },
92 { .n = "pwm_clk", .id = 43 },
93 { .n = "adc_clk", .id = 44 },
104 { .n = "smd_clk", .id = 61 },
[all …]
A Dat91sam9260.c13 u8 id; member
18 u8 id; member
83 { .n = "pioA_clk", .id = 2 },
84 { .n = "pioB_clk", .id = 3 },
85 { .n = "pioC_clk", .id = 4 },
86 { .n = "adc_clk", .id = 5 },
87 { .n = "usart0_clk", .id = 6 },
88 { .n = "usart1_clk", .id = 7 },
89 { .n = "usart2_clk", .id = 8 },
90 { .n = "mci0_clk", .id = 9 },
[all …]
A Dsama5d2.c44 u8 id; member
62 u8 id; member
67 { .n = "matrix1_clk", .id = 14, },
68 { .n = "hsmc_clk", .id = 17, },
106 u8 id; member
108 { .n = "dma0_clk", .id = 6, },
109 { .n = "dma1_clk", .id = 7, },
110 { .n = "aes_clk", .id = 9, },
129 u8 id; member
328 sama5d2_periphck[i].id, in sama5d2_pmc_setup()
[all …]
A Dsama5d3.c44 u8 id; member
62 u8 id; member
66 { .n = "dbgu_clk", .id = 2, },
67 { .n = "hsmc_clk", .id = 5, },
68 { .n = "pioA_clk", .id = 6, },
69 { .n = "pioB_clk", .id = 7, },
70 { .n = "pioC_clk", .id = 8, },
71 { .n = "pioD_clk", .id = 9, },
72 { .n = "pioE_clk", .id = 10, },
89 { .n = "pwm_clk", .id = 28, },
[all …]
A Dsam9x7.c340 u8 id; member
362 u8 id; member
437 u8 id; member
441 .id = 5,
450 .id = 6,
459 .id = 7,
468 .id = 8,
477 .id = 9,
486 .id = 10,
495 .id = 11,
[all …]
A Dat91sam9x5.c45 u8 id; member
68 u8 id; member
72 { .n = "pioAB_clk", .id = 2, },
73 { .n = "pioCD_clk", .id = 3, },
74 { .n = "smd_clk", .id = 4, },
75 { .n = "usart0_clk", .id = 5, },
76 { .n = "usart1_clk", .id = 6, },
98 { .n = "lcdc_clk", .id = 25, },
105 { .n = "isi_clk", .id = 25, },
111 { .n = "lcdc_clk", .id = 25, },
[all …]
/drivers/gpu/drm/amd/display/dc/bios/
A Dbios_parser_common.c67 id = ENUM_ID_1; in enum_id_from_bios_object_id()
70 id = ENUM_ID_2; in enum_id_from_bios_object_id()
73 id = ENUM_ID_3; in enum_id_from_bios_object_id()
76 id = ENUM_ID_4; in enum_id_from_bios_object_id()
79 id = ENUM_ID_5; in enum_id_from_bios_object_id()
82 id = ENUM_ID_6; in enum_id_from_bios_object_id()
85 id = ENUM_ID_7; in enum_id_from_bios_object_id()
92 return id; in enum_id_from_bios_object_id()
169 return id; in encoder_id_from_bios_object_id()
224 return id; in connector_id_from_bios_object_id()
[all …]
/drivers/memory/tegra/
A Dtegra194.c14 .id = TEGRA194_MEMORY_CLIENT_PTCR,
24 .id = TEGRA194_MEMORY_CLIENT_MIU7R,
34 .id = TEGRA194_MEMORY_CLIENT_MIU7W,
44 .id = TEGRA194_MEMORY_CLIENT_HDAR,
74 .id = TEGRA194_MEMORY_CLIENT_SATAR,
104 .id = TEGRA194_MEMORY_CLIENT_HDAW,
124 .id = TEGRA194_MEMORY_CLIENT_SATAW,
134 .id = TEGRA194_MEMORY_CLIENT_ISPRA,
154 .id = TEGRA194_MEMORY_CLIENT_ISPWA,
164 .id = TEGRA194_MEMORY_CLIENT_ISPWB,
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn35/
A Ddcn35_resource.h51 OPP_REG_LIST_DCN10_RI(id), \
52 OPP_DPG_REG_LIST_RI(id), \
57 OPP_REG_LIST_DCN20_RI(id), \
66 SRI_ARR(VPG_MEM_PWR, VPG, id)
81 SRI_ARR(AFMT_CNTL, DIG, id), \
85 SRI_ARR(HDMI_GC, DIG, id), \
125 SRI_ARR(DP_VID_M, DP, id), \
126 SRI_ARR(DP_VID_N, DP, id), \
147 LE_DCN3_REG_LIST_RI(id),\
154 SR_ARR(DIO_LINKF_CNTL, id),\
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_link_encoder.h39 #define AUX_REG_LIST(id)\ argument
44 #define HPD_REG_LIST(id)\ argument
45 SRI(DC_HPD_CONTROL, HPD, id)
54 SRI(DP_CONFIG, DP, id), \
64 SRI(DP_MSE_SAT0, DP, id), \
65 SRI(DP_MSE_SAT1, DP, id), \
66 SRI(DP_MSE_SAT2, DP, id), \
68 SRI(DP_SEC_CNTL, DP, id), \
71 SRI(DP_SEC_CNTL1, DP, id)
88 SRI(DP_CONFIG, DP, id), \
[all …]
/drivers/media/platform/samsung/s3c-camif/
A Dcamif-regs.h65 #define CIGCTRL_IRQ_CLR(id) BIT(19 - (id)) argument
169 #define CIIMGCPT_IMGCPTEN_SC(id) BIT(30 - (id)) argument
171 #define CIIMGCPT_CPT_FREN_ENABLE(id) BIT(25 - (id)) argument
180 #define CIIMGEFF_IE_ENABLE(id) BIT(30 + (id)) argument
196 #define S3C_CAMIF_REG_MSY0SA(id) (0xd4 + ((id) * 0x2c)) argument
197 #define S3C_CAMIF_REG_MSCB0SA(id) (0xd8 + ((id) * 0x2c)) argument
211 #define S3C_CAMIF_REG_MSWIDTH(id) (0xf8 + (id) * 0x2c) argument
218 #define S3C_CAMIF_REG_MSCTRL(id) (0xfc + (id) * 0x2c) argument
232 #define S3C_CAMIF_REG_CISSY(id) (0x12c + (id) * 0x0c) argument
233 #define S3C_CAMIF_REG_CISSCB(id) (0x130 + (id) * 0x0c) argument
[all …]
/drivers/macintosh/
A Dadbhid.c212 int id; member
270 if (!adbhid[id]) { in adbhid_keyboard_input()
409 if (!adbhid[id]) { in adbhid_mouse_input()
762 if (adbhid[id]) { in adbhid_input_register()
927 if (adbhid[id]) { in adbhid_input_reregister()
928 if (adbhid[id]->input->id.product != in adbhid_input_reregister()
937 return 1<<id; in adbhid_input_reregister()
961 int id = keyboard_ids.id[i]; in adbhid_probe() local
985 int id = buttons_ids.id[i]; in adbhid_probe() local
995 int id = mouse_ids.id[i]; in adbhid_probe() local
[all …]
/drivers/interconnect/qcom/
A Dsc8280xp.c21 .id = SC8280XP_MASTER_QSPI_0,
30 .id = SC8280XP_MASTER_QUP_1,
39 .id = SC8280XP_MASTER_QUP_2,
57 .id = SC8280XP_MASTER_IPA,
66 .id = SC8280XP_MASTER_EMAC_1,
75 .id = SC8280XP_MASTER_SDCC_4,
93 .id = SC8280XP_MASTER_USB3_0,
102 .id = SC8280XP_MASTER_USB3_1,
147 .id = SC8280XP_MASTER_QUP_0,
183 .id = SC8280XP_MASTER_SP,
[all …]
A Dsc8180x.c21 .id = SC8180X_MASTER_A1NOC_CFG,
30 .id = SC8180X_MASTER_UFS_CARD,
48 .id = SC8180X_MASTER_UFS_MEM,
57 .id = SC8180X_MASTER_USB3,
66 .id = SC8180X_MASTER_USB3_1,
75 .id = SC8180X_MASTER_USB3_2,
120 .id = SC8180X_MASTER_QUP_0,
165 .id = SC8180X_MASTER_IPA,
174 .id = SC8180X_MASTER_EMAC,
183 .id = SC8180X_MASTER_PCIE,
[all …]
A Dsm8250.c21 .id = SM8250_MASTER_A1NOC_CFG,
30 .id = SM8250_MASTER_QSPI_0,
39 .id = SM8250_MASTER_QUP_1,
48 .id = SM8250_MASTER_QUP_2,
57 .id = SM8250_MASTER_TSIF,
66 .id = SM8250_MASTER_PCIE_2,
75 .id = SM8250_MASTER_SDCC_4,
93 .id = SM8250_MASTER_USB3,
156 .id = SM8250_MASTER_IPA,
165 .id = SM8250_MASTER_PCIE,
[all …]
A Dqcs8300.c20 .id = QCS8300_MASTER_QUP_3,
29 .id = QCS8300_MASTER_EMAC,
38 .id = QCS8300_MASTER_SDC,
47 .id = QCS8300_MASTER_UFS_MEM,
56 .id = QCS8300_MASTER_USB2,
65 .id = QCS8300_MASTER_USB3_0,
83 .id = QCS8300_MASTER_QUP_0,
92 .id = QCS8300_MASTER_QUP_1,
128 .id = QCS8300_MASTER_IPA,
943 .id = QCS8300_SLAVE_PDM,
[all …]
A Dsm8450.c23 .id = SM8450_MASTER_QSPI_0,
32 .id = SM8450_MASTER_QUP_1,
50 .id = SM8450_MASTER_SDCC_4,
59 .id = SM8450_MASTER_UFS_MEM,
68 .id = SM8450_MASTER_USB3_0,
86 .id = SM8450_MASTER_QUP_0,
95 .id = SM8450_MASTER_QUP_2,
122 .id = SM8450_MASTER_IPA,
140 .id = SM8450_MASTER_SP,
405 .id = SM8450_MASTER_MDP,
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
A Ddcn30_dpp.h34 SRI(CM_DEALPHA, CM, id),\
35 SRI(CM_MEM_PWR_STATUS, CM, id),\
36 SRI(CM_BIAS_CR_R, CM, id),\
37 SRI(CM_BIAS_Y_G_CB_B, CM, id),\
38 SRI(PRE_DEGAM, CNVC_CFG, id),\
99 SRI(OTG_H_BLANK, DSCL, id), \
100 SRI(OTG_V_BLANK, DSCL, id), \
101 SRI(SCL_MODE, DSCL, id), \
110 SRI(MPC_SIZE, DSCL, id), \
120 SRI(RECOUT_SIZE, DSCL, id), \
[all …]
/drivers/gpu/drm/i915/display/
A Dintel_dsb_regs.h15 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) argument
16 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) argument
17 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) argument
25 #define DSB_MMIOCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc) argument
31 #define DSB_POLLFUNC(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10) argument
37 #define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14) argument
38 #define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c) argument
39 #define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24) argument
53 #define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28) argument
75 #define DSB_PMCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x38) argument
[all …]

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