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Searched refs:idle (Results 1 – 25 of 165) sorted by relevance

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/drivers/staging/media/atomisp/pci/
A Dsh_css_hrt.c30 bool not_idle = false, idle; in sh_css_hrt_system_is_idle() local
33 idle = sp_ctrl_getbit(SP0_ID, SP_SC_REG, SP_IDLE_BIT); in sh_css_hrt_system_is_idle()
34 not_idle |= !idle; in sh_css_hrt_system_is_idle()
35 if (!idle) in sh_css_hrt_system_is_idle()
38 idle = isp_ctrl_getbit(ISP0_ID, ISP_SC_REG, ISP_IDLE_BIT); in sh_css_hrt_system_is_idle()
39 not_idle |= !idle; in sh_css_hrt_system_is_idle()
40 if (!idle) in sh_css_hrt_system_is_idle()
/drivers/cpuidle/
A DKconfig.arm6 bool "Generic ARM CPU idle Driver"
12 It provides a generic idle driver whose idle states are configured
14 initialized by calling the CPU operations init idle hook
18 bool "PSCI CPU idle Driver"
24 It provides an idle driver that is capable of detecting and
25 managing idle states through the PSCI firmware interface.
29 all idle states are still available.
33 being shared among a group of CPUs (aka cluster idle states).
36 bool "PSCI CPU idle Domain"
44 idle states.
[all …]
A DKconfig5 bool "CPU idle PM support"
10 CPU idle is a generic framework for supporting software-controlled
11 idle processor power management. It includes modular cross-platform
30 This governor implements a simplified idle state selection method
40 This governor implements haltpoll idle state selection, to be
42 for polling for a certain amount of time before entering idle
A DKconfig.riscv7 bool "RISC-V SBI CPU idle Driver"
13 Select this option to enable RISC-V SBI firmware based CPU idle
15 DT based layout of the idle state.
A DKconfig.powerpc11 Select this option to enable processor idle state management
20 Select this option to enable processor idle state management
/drivers/gpu/drm/nouveau/nvkm/engine/gr/
A Dg84.c121 bool idle, timeout = false; in g84_gr_tlb_flush() local
132 idle = true; in g84_gr_tlb_flush()
134 for (tmp = nvkm_rd32(device, 0x400380); tmp && idle; tmp >>= 3) { in g84_gr_tlb_flush()
136 idle = false; in g84_gr_tlb_flush()
139 for (tmp = nvkm_rd32(device, 0x400384); tmp && idle; tmp >>= 3) { in g84_gr_tlb_flush()
141 idle = false; in g84_gr_tlb_flush()
144 for (tmp = nvkm_rd32(device, 0x400388); tmp && idle; tmp >>= 3) { in g84_gr_tlb_flush()
146 idle = false; in g84_gr_tlb_flush()
148 } while (!idle && in g84_gr_tlb_flush()
/drivers/macintosh/
A Dvia-macii.c108 idle, enumerator
154 macii_state = idle; in macii_init()
270 if (macii_state == idle) in macii_write()
291 if (current_req && macii_state == idle) in macii_autopoll()
386 case idle: in macii_interrupt()
475 macii_state = idle; in macii_interrupt()
507 macii_state = idle; in macii_interrupt()
543 if (macii_state == idle) { in macii_interrupt()
550 if (macii_state == idle) { in macii_interrupt()
A Dvia-cuda.c158 idle, enumerator
217 cuda_state = idle; in find_via_cuda()
258 cuda_state = idle; in find_via_cuda()
523 if (cuda_state == idle) in cuda_write()
594 case idle: in cuda_interrupt()
619 cuda_state = idle; in cuda_interrupt()
645 cuda_state = idle; in cuda_interrupt()
711 cuda_state = idle; in cuda_interrupt()
713 if (cuda_state == idle && TREQ_asserted(in_8(&via[B]))) { in cuda_interrupt()
A Dadb-iop.c32 idle, enumerator
65 adb_iop_state = idle; in adb_iop_done()
72 if (adb_iop_state == idle) in adb_iop_done()
241 if (adb_iop_state == idle) in adb_iop_write()
/drivers/gpu/drm/etnaviv/
A Detnaviv_gpu.c534 u32 control, idle; in etnaviv_hw_reset() local
960 u32 dma_lo, dma_hi, axi, idle; in etnaviv_gpu_debugfs() local
1038 seq_printf(m, "\tidle: 0x%08x\n", idle); in etnaviv_gpu_debugfs()
1040 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) in etnaviv_gpu_debugfs()
1042 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) in etnaviv_gpu_debugfs()
1044 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) in etnaviv_gpu_debugfs()
1078 if (idle & VIVS_HI_IDLE_STATE_AXI_LP) in etnaviv_gpu_debugfs()
1686 idle); in etnaviv_gpu_wait_idle()
1974 u32 idle, mask; in etnaviv_gpu_rpm_suspend() local
1984 if (idle != mask) { in etnaviv_gpu_rpm_suspend()
[all …]
/drivers/md/dm-vdo/
A Dphysical-zone.c215 idle_pbn_lock *idle; in return_pbn_lock_to_pool() local
220 idle = container_of(lock, idle_pbn_lock, lock); in return_pbn_lock_to_pool()
221 INIT_LIST_HEAD(&idle->entry); in return_pbn_lock_to_pool()
222 list_add_tail(&idle->entry, &pool->idle_list); in return_pbn_lock_to_pool()
294 idle_pbn_lock *idle; in borrow_pbn_lock_from_pool() local
310 idle = list_entry(idle_entry, idle_pbn_lock, entry); in borrow_pbn_lock_from_pool()
311 idle->lock.holder_count = 0; in borrow_pbn_lock_from_pool()
312 set_pbn_lock_type(&idle->lock, type); in borrow_pbn_lock_from_pool()
314 *lock_ptr = &idle->lock; in borrow_pbn_lock_from_pool()
A Dfunnel-workqueue.c59 atomic_t idle; member
146 if ((atomic_read(&queue->idle) != 1) || (atomic_cmpxchg(&queue->idle, 1, 0) != 1)) in enqueue_work_queue_completion()
190 atomic_set(&queue->idle, 1); in wait_for_next_completion()
217 atomic_set(&queue->idle, 0); in wait_for_next_completion()
484 thread_status = atomic_read(&queue->idle) ? "idle" : "running"; in dump_simple_work_queue()
/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
A Didle.fuc26 process(PROC_IDLE, #idle, #idle_recv)
41 // $r15 - current (idle)
49 // $r15 - current (idle)
51 idle:
83 bra #idle
A Dgf119.fuc444 #include "idle.fuc"
55 #include "idle.fuc"
68 #include "idle.fuc"
A Dgk208.fuc544 #include "idle.fuc"
55 #include "idle.fuc"
68 #include "idle.fuc"
A Dgf100.fuc344 #include "idle.fuc"
55 #include "idle.fuc"
68 #include "idle.fuc"
/drivers/pmdomain/rockchip/
A Dpm-domains.c122 .idle_mask = (idle), \
135 .idle_mask = (idle), \
148 .idle_mask = (idle), \
167 .idle_mask = (idle), \
186 .idle_mask = (idle), \
198 .idle_mask = (idle), \
206 DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup)
230 …DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_ma…
377 bool idle) in rockchip_pmu_set_idle_request() argument
396 pd_info->req_mask, idle ? -1U : 0); in rockchip_pmu_set_idle_request()
[all …]
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_ids.c198 struct amdgpu_vmid **idle, in amdgpu_vmid_grab_idle() argument
218 list_for_each_entry((*idle), &id_mgr->ids_lru, list) { in amdgpu_vmid_grab_idle()
223 fences[i] = amdgpu_sync_peek_fence(&(*idle)->active, r); in amdgpu_vmid_grab_idle()
230 if (&(*idle)->list == &id_mgr->ids_lru) { in amdgpu_vmid_grab_idle()
236 *idle = NULL; in amdgpu_vmid_grab_idle()
405 struct amdgpu_vmid *idle = NULL; in amdgpu_vmid_grab() local
410 r = amdgpu_vmid_grab_idle(ring, &idle, fence); in amdgpu_vmid_grab()
411 if (r || !idle) in amdgpu_vmid_grab()
425 id = idle; in amdgpu_vmid_grab()
/drivers/media/rc/
A Drc-ir-raw.c173 if (dev->idle && !ev->pulse) in ir_raw_event_store_with_filter()
175 else if (dev->idle) in ir_raw_event_store_with_filter()
201 void ir_raw_event_set_idle(struct rc_dev *dev, bool idle) in ir_raw_event_set_idle() argument
206 dev_dbg(&dev->dev, "%s idle mode\n", idle ? "enter" : "leave"); in ir_raw_event_set_idle()
208 if (idle) { in ir_raw_event_set_idle()
215 dev->s_idle(dev, idle); in ir_raw_event_set_idle()
217 dev->idle = idle; in ir_raw_event_set_idle()
624 dev->idle = true; in ir_raw_event_prepare()
A Drc-loopback.c27 bool idle; member
145 if (lodev->idle != enable) { in loop_set_idle()
147 lodev->idle = enable; in loop_set_idle()
248 loopdev.idle = true; in loop_init()
/drivers/i2c/muxes/
A Di2c-mux-gpio.c51 i2c_mux_gpio_set(mux, mux->data.idle); in i2c_mux_gpio_deselect()
120 if (device_property_read_u32(dev, "idle-state", &mux->data.idle)) in i2c_mux_gpio_probe_fw()
121 mux->data.idle = I2C_MUX_GPIO_NO_IDLE; in i2c_mux_gpio_probe_fw()
177 if (mux->data.idle != I2C_MUX_GPIO_NO_IDLE) { in i2c_mux_gpio_probe()
178 initial_state = mux->data.idle; in i2c_mux_gpio_probe()
/drivers/block/
A Dswim3.c45 idle, enumerator
494 case idle: in act()
572 fs->state = idle; in scan_timeout()
595 fs->state = idle; in seek_timeout()
623 fs->state = idle; in settle_timeout()
651 fs->state = idle; in xfer_timeout()
769 fs->state = idle; in swim3_interrupt()
778 fs->state = idle; in swim3_interrupt()
793 fs->state = idle; in swim3_interrupt()
849 fs->state = idle; in release_drive()
[all …]
/drivers/net/wireless/realtek/rtw89/
A Defuse.h21 int rtw89_cnv_efuse_state_ax(struct rtw89_dev *rtwdev, bool idle);
24 int rtw89_cnv_efuse_state_be(struct rtw89_dev *rtwdev, bool idle);
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
A Ddml2_dpmm_dcn4.c181 …in_out->programming->min_clocks.dcn4x.idle.uclk_khz = dml_round_up(min_uclk_avg > min_uclk_latency… in calculate_idle_minimums()
182 …in_out->programming->min_clocks.dcn4x.idle.fclk_khz = dml_round_up(min_fclk_avg > min_fclk_latency… in calculate_idle_minimums()
301 …result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.idle.dcfclk_khz, &state_table->dcfclk… in map_soc_min_clocks_to_dpm_fine_grained()
303 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.idle.fclk_khz, &state_table->fclk); in map_soc_min_clocks_to_dpm_fine_grained()
305 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.idle.uclk_khz, &state_table->uclk); in map_soc_min_clocks_to_dpm_fine_grained()
342 if (display_cfg->min_clocks.dcn4x.idle.dcfclk_khz <= state_table->dcfclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
343 display_cfg->min_clocks.dcn4x.idle.fclk_khz <= state_table->fclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
344 display_cfg->min_clocks.dcn4x.idle.uclk_khz <= state_table->uclk.clk_values_khz[index]) { in map_soc_min_clocks_to_dpm_coarse_grained()
345 display_cfg->min_clocks.dcn4x.idle.dcfclk_khz = state_table->dcfclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
346 display_cfg->min_clocks.dcn4x.idle.fclk_khz = state_table->fclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
[all …]
/drivers/block/zram/
A DKconfig108 bool "Write back incompressible or idle page to backing device"
111 This lets zram entries (incompressible or idle pages) be written
116 With /sys/block/zramX/{idle,writeback}, application could ask
117 idle page's writeback to the backing device to save in memory.

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