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Searched refs:ih (Results 1 – 25 of 61) sorted by relevance

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/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_ih.c52 ih->ptr_mask = ih->ring_size - 1; in amdgpu_ih_ring_init()
53 ih->rptr = 0; in amdgpu_ih_ring_init()
71 ih->wptr_addr = dma_addr + ih->ring_size; in amdgpu_ih_ring_init()
72 ih->wptr_cpu = &ih->ring[ih->ring_size / 4]; in amdgpu_ih_ring_init()
73 ih->rptr_addr = dma_addr + ih->ring_size + 4; in amdgpu_ih_ring_init()
74 ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1]; in amdgpu_ih_ring_init()
90 &ih->ring_obj, &ih->gpu_addr, in amdgpu_ih_ring_init()
129 (void *)ih->ring, ih->gpu_addr); in amdgpu_ih_ring_fini()
132 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, in amdgpu_ih_ring_fini()
228 ih->rptr &= ih->ptr_mask; in amdgpu_ih_process()
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A Dvega20_ih.c145 if (ih == &adev->irq.ih) in vega20_ih_toggle_ring_interrupts()
163 ih->rptr = 0; in vega20_ih_toggle_ring_interrupts()
258 if (ih == &adev->irq.ih) in vega20_ih_enable_ring()
271 if (ih == &adev->irq.ih) { in vega20_ih_enable_ring()
422 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) { in vega20_ih_get_wptr()
452 amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp); in vega20_ih_get_wptr()
488 if ((v < ih->ring_size) && (v != ih->rptr)) in vega20_ih_irq_rearm()
489 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega20_ih_irq_rearm()
513 *ih->rptr_cpu = ih->rptr; in vega20_ih_set_rptr()
514 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega20_ih_set_rptr()
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A Dvega10_ih.c109 if (ih == &adev->irq.ih) in vega10_ih_toggle_ring_interrupts()
127 ih->rptr = 0; in vega10_ih_toggle_ring_interrupts()
222 if (ih == &adev->irq.ih) in vega10_ih_enable_ring()
235 if (ih == &adev->irq.ih) { in vega10_ih_enable_ring()
341 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) { in vega10_ih_get_wptr()
368 amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp); in vega10_ih_get_wptr()
403 if ((v < ih->ring_size) && (v != ih->rptr)) in vega10_ih_irq_rearm()
404 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega10_ih_irq_rearm()
428 *ih->rptr_cpu = ih->rptr; in vega10_ih_set_rptr()
429 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega10_ih_set_rptr()
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A Dnavi10_ih.c165 if (ih == &adev->irq.ih) in navi10_ih_toggle_ring_interrupts()
182 ih->rptr = 0; in navi10_ih_toggle_ring_interrupts()
277 if (ih == &adev->irq.ih) in navi10_ih_enable_ring()
291 if (ih == &adev->irq.ih) { in navi10_ih_enable_ring()
412 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) { in navi10_ih_get_wptr()
438 amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp); in navi10_ih_get_wptr()
473 if ((v < ih->ring_size) && (v != ih->rptr)) in navi10_ih_irq_rearm()
474 WDOORBELL32(ih->doorbell_index, ih->rptr); in navi10_ih_irq_rearm()
498 *ih->rptr_cpu = ih->rptr; in navi10_ih_set_rptr()
499 WDOORBELL32(ih->doorbell_index, ih->rptr); in navi10_ih_set_rptr()
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A Dih_v6_0.c167 if (ih == &adev->irq.ih) in ih_v6_0_toggle_ring_interrupts()
184 ih->rptr = 0; in ih_v6_0_toggle_ring_interrupts()
200 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v6_0_toggle_interrupts() local
279 if (ih == &adev->irq.ih) in ih_v6_0_enable_ring()
295 if (ih == &adev->irq.ih) { in ih_v6_0_enable_ring()
323 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v6_0_irq_init() local
497 if ((v < ih->ring_size) && (v != ih->rptr)) in ih_v6_0_irq_rearm()
498 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v6_0_irq_rearm()
519 *ih->rptr_cpu = ih->rptr; in ih_v6_0_set_rptr()
520 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v6_0_set_rptr()
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A Dih_v6_1.c139 if (ih == &adev->irq.ih) in ih_v6_1_toggle_ring_interrupts()
156 ih->rptr = 0; in ih_v6_1_toggle_ring_interrupts()
172 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v6_1_toggle_interrupts() local
251 if (ih == &adev->irq.ih) in ih_v6_1_enable_ring()
267 if (ih == &adev->irq.ih) { in ih_v6_1_enable_ring()
295 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v6_1_irq_init() local
466 if ((v < ih->ring_size) && (v != ih->rptr)) in ih_v6_1_irq_rearm()
467 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v6_1_irq_rearm()
488 *ih->rptr_cpu = ih->rptr; in ih_v6_1_set_rptr()
489 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v6_1_set_rptr()
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A Dih_v7_0.c139 if (ih == &adev->irq.ih) in ih_v7_0_toggle_ring_interrupts()
156 ih->rptr = 0; in ih_v7_0_toggle_ring_interrupts()
172 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v7_0_toggle_interrupts() local
251 if (ih == &adev->irq.ih) in ih_v7_0_enable_ring()
267 if (ih == &adev->irq.ih) { in ih_v7_0_enable_ring()
295 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v7_0_irq_init() local
465 if ((v < ih->ring_size) && (v != ih->rptr)) in ih_v7_0_irq_rearm()
466 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v7_0_irq_rearm()
485 *ih->rptr_cpu = ih->rptr; in ih_v7_0_set_rptr()
486 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v7_0_set_rptr()
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A Dtonga_ih.c67 adev->irq.ih.enabled = true; in tonga_ih_enable_interrupts()
87 adev->irq.ih.enabled = false; in tonga_ih_disable_interrupts()
88 adev->irq.ih.rptr = 0; in tonga_ih_disable_interrupts()
105 struct amdgpu_ih_ring *ih = &adev->irq.ih; in tonga_ih_irq_init() local
216 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in tonga_ih_get_wptr()
217 ih->rptr = (wptr + 16) & ih->ptr_mask; in tonga_ih_get_wptr()
263 ih->rptr += 16; in tonga_ih_decode_iv()
277 if (ih->use_doorbell) { in tonga_ih_set_rptr()
279 *ih->rptr_cpu = ih->rptr; in tonga_ih_set_rptr()
280 WDOORBELL32(ih->doorbell_index, ih->rptr); in tonga_ih_set_rptr()
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A Damdgpu_ih.h88 u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
89 void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
91 uint64_t (*decode_iv_ts)(struct amdgpu_ih_ring *ih, u32 rptr,
93 void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
96 #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih)) argument
98 (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
99 #define amdgpu_ih_decode_iv_ts(adev, ih, rptr, offset) \ argument
101 (adev)->irq.ih_funcs->decode_iv_ts((ih), (rptr), (offset)))
102 #define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih)) argument
110 struct amdgpu_ih_ring *ih);
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A Dcik_ih.c69 adev->irq.ih.enabled = true; in cik_ih_enable_interrupts()
91 adev->irq.ih.enabled = false; in cik_ih_disable_interrupts()
92 adev->irq.ih.rptr = 0; in cik_ih_disable_interrupts()
108 struct amdgpu_ih_ring *ih = &adev->irq.ih; in cik_ih_irq_init() local
189 struct amdgpu_ih_ring *ih) in cik_ih_get_wptr() argument
202 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cik_ih_get_wptr()
203 ih->rptr = (wptr + 16) & ih->ptr_mask; in cik_ih_get_wptr()
214 return (wptr & ih->ptr_mask); in cik_ih_get_wptr()
253 u32 ring_index = ih->rptr >> 2; in cik_ih_decode_iv()
269 ih->rptr += 16; in cik_ih_decode_iv()
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A Dsi_ih.c45 adev->irq.ih.enabled = true; in si_ih_enable_interrupts()
59 adev->irq.ih.enabled = false; in si_ih_disable_interrupts()
60 adev->irq.ih.rptr = 0; in si_ih_disable_interrupts()
65 struct amdgpu_ih_ring *ih = &adev->irq.ih; in si_ih_irq_init() local
109 struct amdgpu_ih_ring *ih) in si_ih_get_wptr() argument
118 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in si_ih_get_wptr()
119 ih->rptr = (wptr + 16) & ih->ptr_mask; in si_ih_get_wptr()
130 return (wptr & ih->ptr_mask); in si_ih_get_wptr()
137 u32 ring_index = ih->rptr >> 2; in si_ih_decode_iv()
151 ih->rptr += 16; in si_ih_decode_iv()
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A Diceland_ih.c69 adev->irq.ih.enabled = true; in iceland_ih_enable_interrupts()
91 adev->irq.ih.enabled = false; in iceland_ih_disable_interrupts()
92 adev->irq.ih.rptr = 0; in iceland_ih_disable_interrupts()
108 struct amdgpu_ih_ring *ih = &adev->irq.ih; in iceland_ih_irq_init() local
212 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in iceland_ih_get_wptr()
213 ih->rptr = (wptr + 16) & ih->ptr_mask; in iceland_ih_get_wptr()
225 return (wptr & ih->ptr_mask); in iceland_ih_get_wptr()
239 struct amdgpu_ih_ring *ih, in iceland_ih_decode_iv() argument
243 u32 ring_index = ih->rptr >> 2; in iceland_ih_decode_iv()
259 ih->rptr += 16; in iceland_ih_decode_iv()
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A Dcz_ih.c69 adev->irq.ih.enabled = true; in cz_ih_enable_interrupts()
91 adev->irq.ih.enabled = false; in cz_ih_disable_interrupts()
92 adev->irq.ih.rptr = 0; in cz_ih_disable_interrupts()
108 struct amdgpu_ih_ring *ih = &adev->irq.ih; in cz_ih_irq_init() local
191 struct amdgpu_ih_ring *ih) in cz_ih_get_wptr() argument
213 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cz_ih_get_wptr()
214 ih->rptr = (wptr + 16) & ih->ptr_mask; in cz_ih_get_wptr()
226 return (wptr & ih->ptr_mask); in cz_ih_get_wptr()
244 u32 ring_index = ih->rptr >> 2; in cz_ih_decode_iv()
260 ih->rptr += 16; in cz_ih_decode_iv()
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A Damdgpu_irq.c171 ret = amdgpu_ih_process(adev, &adev->irq.ih); in amdgpu_irq_handler()
340 amdgpu_ih_ring_fini(adev, &adev->irq.ih); in amdgpu_irq_fini_hw()
438 struct amdgpu_ih_ring *ih) in amdgpu_irq_dispatch() argument
440 u32 ring_index = ih->rptr >> 2; in amdgpu_irq_dispatch()
447 entry.ih = ih; in amdgpu_irq_dispatch()
448 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index]; in amdgpu_irq_dispatch()
459 trace_amdgpu_iv(ih - &adev->irq.ih, &entry); in amdgpu_irq_dispatch()
498 if (amdgpu_ih_ts_after(ih->processed_timestamp, entry.timestamp)) in amdgpu_irq_dispatch()
499 ih->processed_timestamp = entry.timestamp; in amdgpu_irq_dispatch()
A Damdgpu_irq.h47 struct amdgpu_ih_ring *ih; member
92 struct amdgpu_ih_ring ih, ih1, ih2, ih_soft; member
132 struct amdgpu_ih_ring *ih);
A Damdgpu_trace.h77 TP_PROTO(unsigned ih, struct amdgpu_iv_entry *iv),
78 TP_ARGS(ih, iv),
80 __field(unsigned, ih)
92 __entry->ih = ih;
108 __entry->ih, __entry->client_id, __entry->src_id,
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_irq.c100 void (*ih)(void *), in init_handler_common_data()
104 hcd->handler = ih; in init_handler_common_data()
132 void *ih, in remove_irq_handler() argument
164 if (ih == handler->handler) { in remove_irq_handler()
185 ih, int_params->irq_source, int_params->int_context); in remove_irq_handler()
241 void (*ih)(void *)) in validate_irq_registration_params()
243 if (NULL == int_params || NULL == ih) { in validate_irq_registration_params()
304 void (*ih)(void *), in amdgpu_dm_irq_register_interrupt()
371 void *ih) in amdgpu_dm_irq_unregister_interrupt() argument
388 handler_list = remove_irq_handler(adev, ih, &int_params); in amdgpu_dm_irq_unregister_interrupt()
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/drivers/net/ethernet/sgi/
A Dioc3-eth.c302 struct iphdr *ih; in ioc3_tcpudp_checksum() local
323 if (ip_is_fragment(ih)) in ioc3_tcpudp_checksum()
326 proto = ih->protocol; in ioc3_tcpudp_checksum()
332 (ih->tot_len - (ih->ihl << 2)) + in ioc3_tcpudp_checksum()
333 htons((u16)ih->protocol) + in ioc3_tcpudp_checksum()
334 (ih->saddr >> 16) + (ih->saddr & 0xffff) + in ioc3_tcpudp_checksum()
335 (ih->daddr >> 16) + (ih->daddr & 0xffff); in ioc3_tcpudp_checksum()
996 const struct iphdr *ih = ip_hdr(skb); in ioc3_start_xmit() local
1013 csum = csum_tcpudp_nofold(ih->saddr, ih->daddr, in ioc3_start_xmit()
1014 ih->tot_len - (ih->ihl << 2), in ioc3_start_xmit()
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/drivers/iommu/intel/
A Dcache.c334 u64 addr, unsigned long npages, bool ih, in qi_batch_add_piotlb() argument
345 qi_desc_piotlb(did, pasid, addr, npages, ih, &batch->descs[batch->index]); in qi_batch_add_piotlb()
368 unsigned long mask, int ih) in cache_tag_flush_iotlb() argument
375 pages, ih, domain->qi_batch); in cache_tag_flush_iotlb()
387 ih = 0; in cache_tag_flush_iotlb()
392 qi_batch_add_iotlb(iommu, tag->domain_id, addr | ih, mask, type, in cache_tag_flush_iotlb()
395 __iommu_flush_iotlb(iommu, tag->domain_id, addr | ih, mask, type); in cache_tag_flush_iotlb()
430 unsigned long end, int ih) in cache_tag_flush_range() argument
454 cache_tag_flush_iotlb(domain, tag, addr, pages, mask, ih); in cache_tag_flush_range()
A Diommu.h413 #define QI_IOTLB_IH(ih) (((u64)ih) << 6) argument
439 #define QI_EIOTLB_IH(ih) (((u64)ih) << 6) argument
1103 int ih = 0; in qi_desc_iotlb() local
1113 desc->qw1 = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih) in qi_desc_iotlb()
1139 unsigned long npages, bool ih, in qi_desc_piotlb() argument
1160 QI_EIOTLB_IH(ih) | in qi_desc_piotlb()
1225 unsigned long npages, bool ih);
1301 unsigned long end, int ih);
/drivers/crypto/cavium/nitrox/
A Dnitrox_reqmgr.c450 sr->instr.ih.value = 0; in nitrox_process_se_request()
451 sr->instr.ih.s.g = 1; in nitrox_process_se_request()
452 sr->instr.ih.s.gsz = sr->in.sgmap_cnt; in nitrox_process_se_request()
453 sr->instr.ih.s.ssz = sr->out.sgmap_cnt; in nitrox_process_se_request()
454 sr->instr.ih.s.fsz = FDATA_SIZE + sizeof(struct gphdr); in nitrox_process_se_request()
455 sr->instr.ih.s.tlen = sr->instr.ih.s.fsz + sr->in.total_bytes; in nitrox_process_se_request()
456 sr->instr.ih.bev = cpu_to_be64(sr->instr.ih.value); in nitrox_process_se_request()
/drivers/gpu/drm/radeon/
A Dr600.c3474 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; in r600_ih_ring_init()
3475 rdev->ih.rptr = 0; in r600_ih_ring_init()
3517 if (rdev->ih.ring_obj) { in r600_ih_ring_fini()
3525 rdev->ih.ring = NULL; in r600_ih_ring_fini()
3599 rdev->ih.enabled = true; in r600_enable_interrupts()
3615 rdev->ih.rptr = 0; in r600_disable_interrupts()
3776 if (!rdev->ih.enabled) { in r600_irq_set()
4053 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); in r600_get_ih_wptr()
4054 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in r600_get_ih_wptr()
4116 rptr = rdev->ih.rptr; in r600_irq_process()
[all …]
/drivers/cpufreq/
A Dpmac64-cpufreq.c483 u64 max_freq, min_freq, ih, il; in g5_pm72_cpufreq_init() local
579 ih = *((u32 *)(eeprom + 0x10)); in g5_pm72_cpufreq_init()
583 if (il == ih) { in g5_pm72_cpufreq_init()
590 if (ih != 0 && il != 0) in g5_pm72_cpufreq_init()
591 min_freq = (max_freq * il) / ih; in g5_pm72_cpufreq_init()
/drivers/net/ethernet/marvell/octeon_ep_vf/
A Doctep_vf_main.c602 struct octep_vf_instr_hdr *ih; in octep_vf_start_xmit() local
630 ih = &hw_desc->ih; in octep_vf_start_xmit()
631 ih->tlen = skb->len; in octep_vf_start_xmit()
632 ih->pkind = oct->fw_info.pkind; in octep_vf_start_xmit()
633 ih->fsz = oct->fw_info.fsz; in octep_vf_start_xmit()
634 ih->tlen = skb->len + ih->fsz; in octep_vf_start_xmit()
650 ih->gsz = nr_frags + 1; in octep_vf_start_xmit()
651 ih->gather = 1; in octep_vf_start_xmit()
/drivers/net/ethernet/marvell/octeon_ep/
A Doctep_main.c850 struct octep_instr_hdr *ih; in octep_start_xmit() local
878 ih = &hw_desc->ih; in octep_start_xmit()
879 ih->pkind = oct->conf->fw_info.pkind; in octep_start_xmit()
880 ih->fsz = oct->conf->fw_info.fsz; in octep_start_xmit()
881 ih->tlen = skb->len + ih->fsz; in octep_start_xmit()
897 ih->gsz = nr_frags + 1; in octep_start_xmit()
898 ih->gather = 1; in octep_start_xmit()

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