Searched refs:implementation (Results 1 – 25 of 74) sorted by relevance
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230 u32 implementation = par->Chipset & 0x0ff0; in nv10GetConfig() local261 if (par->twoHeads && (implementation != 0x0110)) { in nv10GetConfig()275 u16 implementation = par->Chipset & 0x0ff0; in NVCommonSetup() local312 (implementation != 0x0100) && in NVCommonSetup()313 (implementation != 0x0150) && in NVCommonSetup()314 (implementation != 0x01A0) && (implementation != 0x0200); in NVCommonSetup()317 (implementation != 0x0110)); in NVCommonSetup()319 par->twoStagePLL = (implementation == 0x0310) || in NVCommonSetup()323 (implementation != 0x0100); in NVCommonSetup()440 if (implementation != 0x0110) { in NVCommonSetup()[all …]
43 Mailbox driver implementation for ASPEED AST27XX SoCs. This driver52 Mailbox driver implementation for Sophgo CV18XX SoCs. This driver73 Mailbox implementation for i.MX Messaging Unit (MU).89 An implementation of the ARM PL320 Interprocessor Communication100 Mailbox implementation for communication with the the firmware109 Mailbox implementation for OMAP family chips with hardware for139 An implementation of the Altera Mailbox soft core. It is used155 Mailbox implementation for STMicroelectonics family chips with163 An implementation of Message Manager slave driver for Keystone216 Mailbox implementation for Microchip devices with an[all …]
18 tristate "I2C bus implementation for Microchip Azurite devices"23 This is I2C bus implementation for Microchip Azurite DPLL/PTP/SyncE30 tristate "SPI bus implementation for Microchip Azurite devices"35 This is SPI bus implementation for Microchip Azurite DPLL/PTP/SyncE
23 DRM connector implementation terminating DRM bridge chains.84 implementation).89 DRM display helpers for HDMI CEC implementation.94 DRM display helpers for HDMI CEC notifiers implementation.
34 tristate "PCI bus implementation for Mellanox Technologies Switch ASICs"39 This is PCI bus implementation for Mellanox Technologies Switch ASICs.45 tristate "I2C bus implementation for Mellanox Technologies Switch ASICs"49 This is I2C bus implementation for Mellanox Technologies Switch ASICs.
23 23:20 implementation as u8, "Implementation version of the architecture";39 ((arch as u32) << Self::IMPLEMENTATION.len()) | u32::from(self.implementation()) in chipset()
62 bool "ARM SMMU QCOM implementation defined debug support"65 Support for implementation specific debug features in ARM SMMU72 or TLB sync timeouts which requires implementation defined
56 return (lock->implementation == &LOCK_IMPLEMENTATIONS[type]); in has_lock_type()72 lock->implementation = &LOCK_IMPLEMENTATIONS[type]; in set_pbn_lock_type()168 lock->implementation->release_reason, in release_pbn_lock_provisional_reference()
29 const struct pbn_lock_implementation *implementation; member
2 tristate "Modem Host Interface (MHI) bus Endpoint implementation"
15 Generic power domain implementation for TI device implementing
18 also using the CONFIG_MIPS_CPS SMP implementation.
20 Support for the PCIe implementation of RISC-V IOMMU architecture.
17 This library includes support for implementation-specific
23 This is implementation of PCI interface support for Marvell Prestera
8 implementation of the Motorola Scalable CAN concept targeted for
15 A userspace implementation can use visl to run a decoding loop even
15 implementation of PSCI_FEATURES(SMCCC_VERSION) which returns
42 complies with the generic implementation of the component without81 that complies with the generic implementation of the component without115 bool "Control implementation defined overflow support in ETM 4.x driver"118 This control provides implementation define control for CoreSight
3 This is an implementation of the NVEC protocol used to communicate with an
16 Modern PCI device implementation. This module implements the25 implementation.95 an appropriate vDPA device implementation that operates on a
21 example for basic implementation of PoDL (802.3bu) specification.
6 - Improve mock manager's implementation, e.g. allocate a block of
9 tristate "Thermal family implementation"15 tristate "Simple 64bit memory family implementation"
24 The VCAP implementation provides switchcore independent handling of rules
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